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| author | David Green <david.green@arm.com> | 2019-09-19 12:17:41 +0000 |
|---|---|---|
| committer | David Green <david.green@arm.com> | 2019-09-19 12:17:41 +0000 |
| commit | 0cfb78e52af247366e6e8fe00a906022bf4abca5 (patch) | |
| tree | d1f6e40aaad275d9a01c98f0d8ee257833b3b4ab /llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp | |
| parent | ec841cf36ca1cb6a154393d7e9f48e8723a38966 (diff) | |
| download | bcm5719-llvm-0cfb78e52af247366e6e8fe00a906022bf4abca5.tar.gz bcm5719-llvm-0cfb78e52af247366e6e8fe00a906022bf4abca5.zip | |
[ARM] MVE i1 splat
We needn't BFI each lane individually into a predicate register when each lane
in the same. A simple sign extend and a vmsr will do.
Differential Revision: https://reviews.llvm.org/D67653
llvm-svn: 372313
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp')
0 files changed, 0 insertions, 0 deletions
