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author | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2015-05-05 19:26:48 +0000 |
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committer | Ulrich Weigand <ulrich.weigand@de.ibm.com> | 2015-05-05 19:26:48 +0000 |
commit | cd808237b24c7d6d0bb7ddf577dba37c31a06a50 (patch) | |
tree | 3e15e263edd31135f4279f6cb05b48dac89ad513 /llvm/lib/Target/SystemZ/SystemZPatterns.td | |
parent | ce4c10958502b8f852dd88496272d262345a2513 (diff) | |
download | bcm5719-llvm-cd808237b24c7d6d0bb7ddf577dba37c31a06a50.tar.gz bcm5719-llvm-cd808237b24c7d6d0bb7ddf577dba37c31a06a50.zip |
[SystemZ] Add CodeGen support for v2f64
This adds ABI and CodeGen support for the v2f64 type, which is natively
supported by z13 instructions.
Based on a patch by Richard Sandiford.
llvm-svn: 236522
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZPatterns.td')
-rw-r--r-- | llvm/lib/Target/SystemZ/SystemZPatterns.td | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZPatterns.td b/llvm/lib/Target/SystemZ/SystemZPatterns.td index e307f8a888e..16a7ed784d7 100644 --- a/llvm/lib/Target/SystemZ/SystemZPatterns.td +++ b/llvm/lib/Target/SystemZ/SystemZPatterns.td @@ -153,3 +153,17 @@ multiclass CompareZeroFP<Instruction insn, RegisterOperand cls> { // The sign of the zero makes no difference. def : Pat<(z_fcmp cls:$reg, (fpimmneg0)), (insn cls:$reg, cls:$reg)>; } + +// Use INSN for performing binary operation OPERATION of type VT +// on registers of class CLS. +class BinaryRRWithType<Instruction insn, RegisterOperand cls, + SDPatternOperator operator, ValueType vt> + : Pat<(vt (operator cls:$x, cls:$y)), (insn cls:$x, cls:$y)>; + +// Use INSN to perform conversion operation OPERATOR, with the input being +// TR2 and the output being TR1. SUPPRESS is 4 to suppress inexact conditions +// and 0 to allow them. MODE is the rounding mode to use. +class FPConversion<Instruction insn, SDPatternOperator operator, TypedReg tr1, + TypedReg tr2, bits<3> suppress, bits<4> mode> + : Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))), + (insn tr2.op:$vec, suppress, mode)>; |