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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-25 09:04:52 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-25 09:04:52 +0000
commit09a8cf3604a6868d56958503cfd6b9087c78cbb9 (patch)
tree02dff2d4ffa803ca3c748f5d4fdf5452c4b62c6b /llvm/lib/Target/SystemZ/SystemZPatterns.td
parenta68e6f5660b725dc695c0b4dfbb0a4f2de332284 (diff)
downloadbcm5719-llvm-09a8cf3604a6868d56958503cfd6b9087c78cbb9.tar.gz
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[SystemZ] Add LOC and LOCG
As with the stores, these instructions can trap when the condition is false, so they are only used for things like (cond ? x : *ptr). llvm-svn: 187112
Diffstat (limited to 'llvm/lib/Target/SystemZ/SystemZPatterns.td')
-rw-r--r--llvm/lib/Target/SystemZ/SystemZPatterns.td12
1 files changed, 12 insertions, 0 deletions
diff --git a/llvm/lib/Target/SystemZ/SystemZPatterns.td b/llvm/lib/Target/SystemZ/SystemZPatterns.td
index 74cc5f019a8..4e4386a3984 100644
--- a/llvm/lib/Target/SystemZ/SystemZPatterns.td
+++ b/llvm/lib/Target/SystemZ/SystemZPatterns.td
@@ -54,6 +54,18 @@ multiclass RMWIByte<SDPatternOperator operator, AddressingMode mode,
def : RMWI<anyextloadi8, operator, truncstorei8, mode, imm64, insn>;
}
+// Record that INSN conditionally performs load operation LOAD into a
+// register of class CLS. The load may trap even if the condition is false.
+multiclass CondLoad<Instruction insn, RegisterOperand cls,
+ SDPatternOperator load> {
+ def : Pat<(z_select_ccmask (load bdaddr20only:$addr), cls:$new, uimm8zx4:$cc),
+ (insn cls:$new, bdaddr20only:$addr, uimm8zx4:$cc)>,
+ Requires<[FeatureLoadStoreOnCond]>;
+ def : Pat<(z_select_ccmask cls:$new, (load bdaddr20only:$addr), uimm8zx4:$cc),
+ (insn cls:$new, bdaddr20only:$addr, (INVCC uimm8zx4:$cc))>,
+ Requires<[FeatureLoadStoreOnCond]>;
+}
+
// Record that INSN performs insertion TYPE into a register of class CLS.
// The inserted operand is loaded using LOAD from an address of mode MODE.
multiclass InsertMem<string type, Instruction insn, RegisterOperand cls,
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