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authorAlex Bradbury <asb@lowrisc.org>2017-09-07 11:30:55 +0000
committerAlex Bradbury <asb@lowrisc.org>2017-09-07 11:30:55 +0000
commitc09d5611c4b0bdbb04cfa3e0d2add61cdad547a2 (patch)
tree2d55ff6db5faf8e53dbee3c868e4414ee1683dd5 /llvm/lib/Target/Sparc
parent6823c5f0c0afd8b21f7704f79bed0fce057534d2 (diff)
downloadbcm5719-llvm-c09d5611c4b0bdbb04cfa3e0d2add61cdad547a2.tar.gz
bcm5719-llvm-c09d5611c4b0bdbb04cfa3e0d2add61cdad547a2.zip
[Sparc][NFC] Clean up SelectCC lowering
The ARM, BPF, MSP430, Sparc and Mips backends all use a similar code sequence for lowering SelectCC. As pointed out by @reames in D29937, this code isn't particularly clear and in most of these backends doesn't actually match the comments. This patch makes the code sequence clearer for the Sparc backend through better variable naming and more accurate comments (e.g. we are inserting triangle control flow, _not_ diamond). There is no functional change. Differential Revision: https://reviews.llvm.org/D37194 llvm-svn: 312713
Diffstat (limited to 'llvm/lib/Target/Sparc')
-rw-r--r--llvm/lib/Target/Sparc/SparcISelLowering.cpp84
1 files changed, 40 insertions, 44 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 422f5aba8da..d011ec87bac 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -3132,57 +3132,53 @@ SparcTargetLowering::expandSelectCC(MachineInstr &MI, MachineBasicBlock *BB,
DebugLoc dl = MI.getDebugLoc();
unsigned CC = (SPCC::CondCodes)MI.getOperand(3).getImm();
- // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
- // control-flow pattern. The incoming instruction knows the destination vreg
- // to set, the condition code register to branch on, the true/false values to
- // select between, and a branch opcode to use.
+ // To "insert" a SELECT_CC instruction, we actually have to insert the
+ // triangle control-flow pattern. The incoming instruction knows the
+ // destination vreg to set, the condition code register to branch on, the
+ // true/false values to select between, and the condition code for the branch.
+ //
+ // We produce the following control flow:
+ // ThisMBB
+ // | \
+ // | IfFalseMBB
+ // | /
+ // SinkMBB
const BasicBlock *LLVM_BB = BB->getBasicBlock();
MachineFunction::iterator It = ++BB->getIterator();
- // thisMBB:
- // ...
- // TrueVal = ...
- // [f]bCC copy1MBB
- // fallthrough --> copy0MBB
- MachineBasicBlock *thisMBB = BB;
+ MachineBasicBlock *ThisMBB = BB;
MachineFunction *F = BB->getParent();
- MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
- MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
- F->insert(It, copy0MBB);
- F->insert(It, sinkMBB);
-
- // Transfer the remainder of BB and its successor edges to sinkMBB.
- sinkMBB->splice(sinkMBB->begin(), BB,
- std::next(MachineBasicBlock::iterator(MI)),
- BB->end());
- sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
-
- // Add the true and fallthrough blocks as its successors.
- BB->addSuccessor(copy0MBB);
- BB->addSuccessor(sinkMBB);
-
- BuildMI(BB, dl, TII.get(BROpcode)).addMBB(sinkMBB).addImm(CC);
-
- // copy0MBB:
- // %FalseValue = ...
- // # fallthrough to sinkMBB
- BB = copy0MBB;
-
- // Update machine-CFG edges
- BB->addSuccessor(sinkMBB);
-
- // sinkMBB:
- // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
- // ...
- BB = sinkMBB;
- BuildMI(*BB, BB->begin(), dl, TII.get(SP::PHI), MI.getOperand(0).getReg())
- .addReg(MI.getOperand(2).getReg())
- .addMBB(copy0MBB)
+ MachineBasicBlock *IfFalseMBB = F->CreateMachineBasicBlock(LLVM_BB);
+ MachineBasicBlock *SinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
+ F->insert(It, IfFalseMBB);
+ F->insert(It, SinkMBB);
+
+ // Transfer the remainder of ThisMBB and its successor edges to SinkMBB.
+ SinkMBB->splice(SinkMBB->begin(), ThisMBB,
+ std::next(MachineBasicBlock::iterator(MI)), ThisMBB->end());
+ SinkMBB->transferSuccessorsAndUpdatePHIs(ThisMBB);
+
+ // Set the new successors for ThisMBB.
+ ThisMBB->addSuccessor(IfFalseMBB);
+ ThisMBB->addSuccessor(SinkMBB);
+
+ BuildMI(ThisMBB, dl, TII.get(BROpcode))
+ .addMBB(SinkMBB)
+ .addImm(CC);
+
+ // IfFalseMBB just falls through to SinkMBB.
+ IfFalseMBB->addSuccessor(SinkMBB);
+
+ // %Result = phi [ %TrueValue, ThisMBB ], [ %FalseValue, IfFalseMBB ]
+ BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
+ MI.getOperand(0).getReg())
.addReg(MI.getOperand(1).getReg())
- .addMBB(thisMBB);
+ .addMBB(ThisMBB)
+ .addReg(MI.getOperand(2).getReg())
+ .addMBB(IfFalseMBB);
MI.eraseFromParent(); // The pseudo instruction is gone now.
- return BB;
+ return SinkMBB;
}
MachineBasicBlock *
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