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authorJakob Stoklund Olesen <stoklund@2pi.dk>2010-04-05 03:10:20 +0000
committerJakob Stoklund Olesen <stoklund@2pi.dk>2010-04-05 03:10:20 +0000
commitb93331f3be8f009b17c3114d5991476157264688 (patch)
treead959ff89fbfde60b3fcaa19019fa95b28016ca5 /llvm/lib/Target/Sparc
parentab5dc34351c8f64ed8f59d8deadf8472830d5771 (diff)
downloadbcm5719-llvm-b93331f3be8f009b17c3114d5991476157264688.tar.gz
bcm5719-llvm-b93331f3be8f009b17c3114d5991476157264688.zip
Replace TSFlagsFields and TSFlagsShifts with a simpler TSFlags field.
When a target instruction wants to set target-specific flags, it should simply set bits in the TSFlags bit vector defined in the Instruction TableGen class. This works well because TableGen resolves member references late: class I : Instruction { AddrMode AM = AddrModeNone; let TSFlags{3-0} = AM.Value; } let AM = AddrMode4 in def ADD : I; TSFlags gets the expected bits from AddrMode4 in this example. llvm-svn: 100384
Diffstat (limited to 'llvm/lib/Target/Sparc')
-rw-r--r--llvm/lib/Target/Sparc/Sparc.td6
1 files changed, 1 insertions, 5 deletions
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
index 53ea8f4a35f..925d782d988 100644
--- a/llvm/lib/Target/Sparc/Sparc.td
+++ b/llvm/lib/Target/Sparc/Sparc.td
@@ -38,11 +38,7 @@ include "SparcRegisterInfo.td"
include "SparcCallingConv.td"
include "SparcInstrInfo.td"
-def SparcInstrInfo : InstrInfo {
- // Define how we want to layout our target-specific information field.
- let TSFlagsFields = [];
- let TSFlagsShifts = [];
-}
+def SparcInstrInfo : InstrInfo;
//===----------------------------------------------------------------------===//
// SPARC processors supported.
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