Remove getAllocatedRegNum(). Use getReg() instead.

llvm-svn: 11393

8 files changed, 15 insertions, 17 deletions

diff --git a/llvm/lib/Target/Sparc/EmitAssembly.cpp b/llvm/lib/Target/Sparc/EmitAssembly.cpp
index 20fbfa3619c..e87f6a2215a 100644
--- a/llvm/lib/Target/Sparc/EmitAssembly.cpp
+++ b/llvm/lib/Target/Sparc/EmitAssembly.cpp
@@ -637,7 +637,7 @@ SparcAsmPrinter::printOneOperand(const MachineOperand &mop,
     case MachineOperand::MO_CCRegister:
     case MachineOperand::MO_MachineRegister:
       {
-        int regNum = (int)mop.getAllocatedRegNum();
+        int regNum = (int)mop.getReg();
         
         if (regNum == Target.getRegInfo().getInvalidRegNum()) {
           // better to print code with NULL registers than to die
diff --git a/llvm/lib/Target/Sparc/InstrSelection/InstrSelectionSupport.cpp b/llvm/lib/Target/Sparc/InstrSelection/InstrSelectionSupport.cpp
index 131107b991e..a7923862cfa 100644
--- a/llvm/lib/Target/Sparc/InstrSelection/InstrSelectionSupport.cpp
+++ b/llvm/lib/Target/Sparc/InstrSelection/InstrSelectionSupport.cpp
@@ -71,7 +71,8 @@ ChooseRegOrImmed(int64_t intValue,
       opType = isSigned? MachineOperand::MO_SignExtendedImmed
                        : MachineOperand::MO_UnextendedImmed;
       getImmedValue = intValue;
-  } else if (intValue == 0 && target.getRegInfo().getZeroRegNum() >= 0) {
+  } else if (intValue == 0 &&
+             target.getRegInfo().getZeroRegNum() != (unsigned)-1) {
     opType = MachineOperand::MO_MachineRegister;
     getMachineRegNum = target.getRegInfo().getZeroRegNum();
   }
diff --git a/llvm/lib/Target/Sparc/PeepholeOpts.cpp b/llvm/lib/Target/Sparc/PeepholeOpts.cpp
index a69171c604e..d8a5515c72d 100644
--- a/llvm/lib/Target/Sparc/PeepholeOpts.cpp
+++ b/llvm/lib/Target/Sparc/PeepholeOpts.cpp
@@ -63,16 +63,15 @@ DeleteInstruction(MachineBasicBlock& mvec,
 static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
   if (MI->getOpcode() == V9::FMOVS || MI->getOpcode() == V9::FMOVD) {
     return (// both operands are allocated to the same register
-            MI->getOperand(0).getAllocatedRegNum() == 
-            MI->getOperand(1).getAllocatedRegNum());
+            MI->getOperand(0).getReg() ==  MI->getOperand(1).getReg());
   } else if (MI->getOpcode() == V9::ADDr || MI->getOpcode() == V9::ORr ||
              MI->getOpcode() == V9::ADDi || MI->getOpcode() == V9::ORi) {
     unsigned srcWithDestReg;
     
     for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
       if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
-          MI->getOperand(srcWithDestReg).getAllocatedRegNum()
-          == MI->getOperand(2).getAllocatedRegNum())
+          MI->getOperand(srcWithDestReg).getReg()
+          == MI->getOperand(2).getReg())
         break;
     
     if (srcWithDestReg == 2)
@@ -82,7 +81,7 @@ static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
       unsigned otherOp = 1 - srcWithDestReg;
       return (// either operand otherOp is register %g0
               (MI->getOperand(otherOp).hasAllocatedReg() &&
-               MI->getOperand(otherOp).getAllocatedRegNum() ==
+               MI->getOperand(otherOp).getReg() ==
                target.getRegInfo().getZeroRegNum()) ||
               
               // or operand otherOp == 0
diff --git a/llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp b/llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp
index f28ca86c708..100f9eb4c62 100644
--- a/llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp
+++ b/llvm/lib/Target/Sparc/RegAlloc/LiveRangeInfo.cpp
@@ -194,9 +194,8 @@ void LiveRangeInfo::constructLiveRanges() {
           // set it directly in the LiveRange
           if (OpI.getMachineOperand().hasAllocatedReg()) {
             unsigned getClassId;
-            LR->setColor(MRI.getClassRegNum(
-                                OpI.getMachineOperand().getAllocatedRegNum(),
-                                getClassId));
+            LR->setColor(MRI.getClassRegNum(OpI.getMachineOperand().getReg(),
+                                            getClassId));
           }
 	}
 
@@ -212,7 +211,7 @@ void LiveRangeInfo::constructLiveRanges() {
           if (MInst->getImplicitOp(i).hasAllocatedReg()) {
             unsigned getClassId;
             LR->setColor(MRI.getClassRegNum(
-                                MInst->getImplicitOp(i).getAllocatedRegNum(),
+                                MInst->getImplicitOp(i).getReg(),
                                 getClassId));
           }
 	}
diff --git a/llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp b/llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp
index 4a7d503f5b2..cc019b478a7 100644
--- a/llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp
+++ b/llvm/lib/Target/Sparc/RegAlloc/PhyRegAlloc.cpp
@@ -1019,12 +1019,11 @@ void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC, int RegType,
   // explicit and implicit operands are set.
   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
     if (MI->getOperand(i).hasAllocatedReg())
-      markRegisterUsed(MI->getOperand(i).getAllocatedRegNum(), RC, RegType,MRI);
+      markRegisterUsed(MI->getOperand(i).getReg(), RC, RegType,MRI);
 
   for (unsigned i = 0, e = MI->getNumImplicitRefs(); i != e; ++i)
     if (MI->getImplicitOp(i).hasAllocatedReg())
-      markRegisterUsed(MI->getImplicitOp(i).getAllocatedRegNum(), RC,
-                       RegType,MRI);
+      markRegisterUsed(MI->getImplicitOp(i).getReg(), RC, RegType,MRI);
 
   // Add all of the scratch registers that are used to save values across the
   // instruction (e.g., for saving state register values).
diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
index 5033a0aaa00..8d6e6d5ad72 100644
--- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp
+++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp
@@ -52,7 +52,7 @@ SparcRegInfo::SparcRegInfo(const SparcTargetMachine &tgt)
 // getZeroRegNum - returns the register that contains always zero.
 // this is the unified register number
 //
-int SparcRegInfo::getZeroRegNum() const {
+unsigned SparcRegInfo::getZeroRegNum() const {
   return getUnifiedRegNum(SparcRegInfo::IntRegClassID,
                           SparcIntRegClass::g0);
 }
diff --git a/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp b/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
index 753f5d30f3d..0db45e3e833 100644
--- a/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
+++ b/llvm/lib/Target/Sparc/SparcV9CodeEmitter.cpp
@@ -661,7 +661,7 @@ int64_t SparcV9CodeEmitter::getMachineOpValue(MachineInstr &MI,
     // This is necessary because the Sparc backend doesn't actually lay out
     // registers in the real fashion -- it skips those that it chooses not to
     // allocate, i.e. those that are the FP, SP, etc.
-    unsigned fakeReg = MO.getAllocatedRegNum();
+    unsigned fakeReg = MO.getReg();
     unsigned realRegByClass = getRealRegNum(fakeReg, MI);
     DEBUG(std::cerr << MO << ": Reg[" << std::dec << fakeReg << "] => "
                     << realRegByClass << " (LLC: " 
diff --git a/llvm/lib/Target/Sparc/SparcV9RegInfo.h b/llvm/lib/Target/Sparc/SparcV9RegInfo.h
index 34069d82f12..3dd9e683e03 100644
--- a/llvm/lib/Target/Sparc/SparcV9RegInfo.h
+++ b/llvm/lib/Target/Sparc/SparcV9RegInfo.h
@@ -86,7 +86,7 @@ public:
   // getZeroRegNum - returns the register that contains always zero this is the
   // unified register number
   //
-  virtual int getZeroRegNum() const;
+  virtual unsigned getZeroRegNum() const;
 
   // getCallAddressReg - returns the reg used for pushing the address when a
   // function is called. This can be used for other purposes between calls