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| author | Joerg Sonnenberger <joerg@bec.de> | 2019-04-23 15:15:33 +0000 |
|---|---|---|
| committer | Joerg Sonnenberger <joerg@bec.de> | 2019-04-23 15:15:33 +0000 |
| commit | 6e7cc49d5cb31ee09b07252b6641d7c94977fd12 (patch) | |
| tree | be29fc709628faf436f51aaa28a38ad3b8147d16 /llvm/lib/Target/Sparc | |
| parent | a2470a4653174067491618b18a8ae596f179cefb (diff) | |
| download | bcm5719-llvm-6e7cc49d5cb31ee09b07252b6641d7c94977fd12.tar.gz bcm5719-llvm-6e7cc49d5cb31ee09b07252b6641d7c94977fd12.zip | |
[SPARC] Use the correct register set for the "r" asm constraint.
64bit mode must use 64bit registers, otherwise assumptions about the top
half of the registers are made. Problem found by Takeshi Nakayama in
NetBSD.
llvm-svn: 358998
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 05c6cce19d3..a6d440fa8aa 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -3258,6 +3258,8 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, case 'r': if (VT == MVT::v2i32) return std::make_pair(0U, &SP::IntPairRegClass); + else if (Subtarget->is64Bit()) + return std::make_pair(0U, &SP::I64RegsRegClass); else return std::make_pair(0U, &SP::IntRegsRegClass); case 'f': |
