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| author | Daniel Cederman <cederman@gaisler.com> | 2018-07-16 12:16:53 +0000 |
|---|---|---|
| committer | Daniel Cederman <cederman@gaisler.com> | 2018-07-16 12:16:53 +0000 |
| commit | 68765757d4e952faaeda6f2402ecfb464b288859 (patch) | |
| tree | 7a9e666148baf608b723880804efbed6264da9f2 /llvm/lib/Target/Sparc | |
| parent | 1d20cc20f672ed7eb5f94584905ba6e902f669eb (diff) | |
| download | bcm5719-llvm-68765757d4e952faaeda6f2402ecfb464b288859.tar.gz bcm5719-llvm-68765757d4e952faaeda6f2402ecfb464b288859.zip | |
[Sparc] Generate ta 1 for the @llvm.debugtrap intrinsic
Summary: Software trap number one is the trap used for breakpoints
in the Sparc ABI.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48637
llvm-svn: 337163
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.td | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index 14a99c085f8..1a42b235832 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1727,6 +1727,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, setOperationAction(ISD::VAARG , MVT::Other, Custom); setOperationAction(ISD::TRAP , MVT::Other, Legal); + setOperationAction(ISD::DEBUGTRAP , MVT::Other, Legal); // Use the default implementation. setOperationAction(ISD::VACOPY , MVT::Other, Expand); diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index ad00c83171d..7541e3e2c60 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1009,6 +1009,9 @@ let DecoderNamespace = "SparcV9", DecoderMethod = "DecodeTRAP", Predicates = [Ha let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>; +def : Pat<(debugtrap), + (TRAPri (i32 G0), (i32 1), (i32 8))>; + // Section B.28 - Read State Register Instructions let rs2 = 0 in def RDASR : F3_1<2, 0b101000, |
