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| author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-18 22:38:52 +0000 |
|---|---|---|
| committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-18 22:38:52 +0000 |
| commit | 5f629318fa7da04a2594658e9ba3c01b62463e2b (patch) | |
| tree | e0ae5f2148e974e2beb580f6e6a118292c47ce4c /llvm/lib/Target/Sparc | |
| parent | 0a2990a7c6282429af973e9c539b9991869dfbc9 (diff) | |
| download | bcm5719-llvm-5f629318fa7da04a2594658e9ba3c01b62463e2b.tar.gz bcm5719-llvm-5f629318fa7da04a2594658e9ba3c01b62463e2b.zip | |
Added support for condition code loading/stroing in methods cpReg2Reg etc.
llvm-svn: 911
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcRegClassInfo.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcRegInfo.cpp | 6 |
2 files changed, 8 insertions, 2 deletions
diff --git a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp index ff01f355edc..3ff0779b588 100644 --- a/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegClassInfo.cpp @@ -42,7 +42,7 @@ void SparcIntRegClass::colorIGNode(IGNode * Node, bool IsColorUsedArr[]) const LR->setColor( LR->getSuggestedColor() ); return; } - else { // can't allocate the suggested col + else if ( DEBUG_RA ) { // can't allocate the suggested col cerr << " Could NOT allocate the suggested color for LR "; LR->printSet(); cerr << endl; } @@ -192,7 +192,7 @@ void SparcFloatRegClass::colorIGNode(IGNode * Node,bool IsColorUsedArr[]) const LR->setColor( LR->getSuggestedColor() ); return; } - else { // can't allocate the suggested col + else if (DEBUG_RA) { // can't allocate the suggested col cerr << " Could NOT allocate the suggested color for LR "; LR->printSet(); cerr << endl; } diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp index 5756dc32fcb..60f4203c38c 100644 --- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp @@ -621,6 +621,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg, switch( RegType ) { case IntRegType: + case IntCCRegType: + case FloatCCRegType: MI = new MachineInstr(ADD, 3); MI->SetMachineOperand(0, SrcReg, false); MI->SetMachineOperand(1, SparcIntRegOrder::g0, false); @@ -664,6 +666,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg, switch( RegType ) { case IntRegType: + case IntCCRegType: + case FloatCCRegType: MI = new MachineInstr(STX, 3); MI->SetMachineOperand(0, DestPtrReg, false); MI->SetMachineOperand(1, SrcReg, false); @@ -711,6 +715,8 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg, switch( RegType ) { case IntRegType: + case IntCCRegType: + case FloatCCRegType: MI = new MachineInstr(LDX, 3); MI->SetMachineOperand(0, SrcPtrReg, false); MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed, |
