Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an

extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714

1 files changed, 4 insertions, 4 deletions

diff --git a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 1d1b595743c..801cf4ec9bf 100644
--- a/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -137,6 +137,9 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
   addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
   addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
 
+  // Turn FP extload into load/fextend
+  setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+  
   // Custom legalize GlobalAddress nodes into LO/HI parts.
   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
   setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
@@ -161,9 +164,6 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
   setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
   setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
   
-  // Turn FP extload into load/fextend
-  setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
-  
   // Sparc has no select or setcc: expand to SELECT_CC.
   setOperationAction(ISD::SELECT, MVT::i32, Expand);
   setOperationAction(ISD::SELECT, MVT::f32, Expand);
@@ -332,7 +332,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         if (ObjectVT == MVT::i32) {
           Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
         } else {
-          unsigned LoadOp =
+          ISD::LoadExtType LoadOp =
             I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
 
           // Sparc is big endian, so add an offset based on the ObjectVT.