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| author | Daniel Cederman <cederman@gaisler.com> | 2016-11-28 15:33:03 +0000 |
|---|---|---|
| committer | Daniel Cederman <cederman@gaisler.com> | 2016-11-28 15:33:03 +0000 |
| commit | 59168e28e0df97eb39e037a376a73ffbf4c06e01 (patch) | |
| tree | 786a7108b54dcfccbdd26fe2ec6e354c666ae756 /llvm/lib/Target/Sparc | |
| parent | a41336179898a510ade14804d71a68386aa7d485 (diff) | |
| download | bcm5719-llvm-59168e28e0df97eb39e037a376a73ffbf4c06e01.tar.gz bcm5719-llvm-59168e28e0df97eb39e037a376a73ffbf4c06e01.zip | |
Test commit
llvm-svn: 288036
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcRegisterInfo.td | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.td b/llvm/lib/Target/Sparc/SparcRegisterInfo.td index d1ef3b19dca..6ecfddfc7d6 100644 --- a/llvm/lib/Target/Sparc/SparcRegisterInfo.td +++ b/llvm/lib/Target/Sparc/SparcRegisterInfo.td @@ -331,7 +331,6 @@ def IntRegs : RegisterClass<"SP", [i32, i64], 32, (sequence "L%u", 0, 7), (sequence "O%u", 0, 7))>; - // Should be in the same order as IntRegs. def IntPair : RegisterClass<"SP", [v2i32], 64, (add I0_I1, I2_I3, I4_I5, I6_I7, |
