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| author | Michael Kuperstein <mkuper@google.com> | 2016-08-18 20:08:15 +0000 |
|---|---|---|
| committer | Michael Kuperstein <mkuper@google.com> | 2016-08-18 20:08:15 +0000 |
| commit | 2bc3d4d46c5f19d8433fd088fa95d18f9707bde8 (patch) | |
| tree | 1bf251351a4472649c63fb3f1bc7f2f056386f1f /llvm/lib/Target/Sparc | |
| parent | dea5ccb04b8be312456a5bdb6483cfb0fcb5b962 (diff) | |
| download | bcm5719-llvm-2bc3d4d46c5f19d8433fd088fa95d18f9707bde8.tar.gz bcm5719-llvm-2bc3d4d46c5f19d8433fd088fa95d18f9707bde8.zip | |
[SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround
The names of the tablegen defs now match the names of the ISD nodes.
This makes the world a slightly saner place, as previously "fround" matched
ISD::FP_ROUND and not ISD::FROUND.
Differential Revision: https://reviews.llvm.org/D23597
llvm-svn: 279129
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcISelLowering.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.td | 20 |
2 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp index a043d1102a7..3d743448e79 100644 --- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp +++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp @@ -1508,7 +1508,7 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM, // AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); } - // Turn FP extload into load/fextend + // Turn FP extload into load/fpextend for (MVT VT : MVT::fp_valuetypes()) { setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand); setLoadExtAction(ISD::EXTLOAD, VT, MVT::f64, Expand); diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index cc55c9c8e03..00d22cb286d 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -1131,32 +1131,32 @@ def FQTOI : F3_3u<2, 0b110100, 0b011010011, def FSTOD : F3_3u<2, 0b110100, 0b011001001, (outs DFPRegs:$rd), (ins FPRegs:$rs2), "fstod $rs2, $rd", - [(set f64:$rd, (fextend f32:$rs2))], + [(set f64:$rd, (fpextend f32:$rs2))], IIC_fpu_stod>; def FSTOQ : F3_3u<2, 0b110100, 0b011001101, (outs QFPRegs:$rd), (ins FPRegs:$rs2), "fstoq $rs2, $rd", - [(set f128:$rd, (fextend f32:$rs2))]>, + [(set f128:$rd, (fpextend f32:$rs2))]>, Requires<[HasHardQuad]>; def FDTOS : F3_3u<2, 0b110100, 0b011000110, (outs FPRegs:$rd), (ins DFPRegs:$rs2), "fdtos $rs2, $rd", - [(set f32:$rd, (fround f64:$rs2))], + [(set f32:$rd, (fpround f64:$rs2))], IIC_fpu_fast_instr>; def FDTOQ : F3_3u<2, 0b110100, 0b011001110, (outs QFPRegs:$rd), (ins DFPRegs:$rs2), "fdtoq $rs2, $rd", - [(set f128:$rd, (fextend f64:$rs2))]>, + [(set f128:$rd, (fpextend f64:$rs2))]>, Requires<[HasHardQuad]>; def FQTOS : F3_3u<2, 0b110100, 0b011000111, (outs FPRegs:$rd), (ins QFPRegs:$rs2), "fqtos $rs2, $rd", - [(set f32:$rd, (fround f128:$rs2))]>, + [(set f32:$rd, (fpround f128:$rs2))]>, Requires<[HasHardQuad]>; def FQTOD : F3_3u<2, 0b110100, 0b011001011, (outs DFPRegs:$rd), (ins QFPRegs:$rs2), "fqtod $rs2, $rd", - [(set f64:$rd, (fround f128:$rs2))]>, + [(set f64:$rd, (fpround f128:$rs2))]>, Requires<[HasHardQuad]>; // Floating-point Move Instructions, p. 144 @@ -1255,14 +1255,14 @@ let Predicates = [HasNoFsmuldFix] in def FSMULD : F3_3<2, 0b110100, 0b001101001, (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2), "fsmuld $rs1, $rs2, $rd", - [(set f64:$rd, (fmul (fextend f32:$rs1), - (fextend f32:$rs2)))], + [(set f64:$rd, (fmul (fpextend f32:$rs1), + (fpextend f32:$rs2)))], IIC_fpu_muld>; def FDMULQ : F3_3<2, 0b110100, 0b001101110, (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2), "fdmulq $rs1, $rs2, $rd", - [(set f128:$rd, (fmul (fextend f64:$rs1), - (fextend f64:$rs2)))]>, + [(set f128:$rd, (fmul (fpextend f64:$rs1), + (fpextend f64:$rs2)))]>, Requires<[HasHardQuad]>; // FDIVS generates an erratum on LEON processors, so by disabling this instruction |
