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| author | Douglas Katzman <dougk@google.com> | 2015-08-19 19:30:57 +0000 |
|---|---|---|
| committer | Douglas Katzman <dougk@google.com> | 2015-08-19 19:30:57 +0000 |
| commit | 2362b69dd9e1ad3b5be54780b051bb0f3860853f (patch) | |
| tree | 44b1852ecaa89944ede9587e351e718d82f4c054 /llvm/lib/Target/Sparc | |
| parent | 5cedc8fbfaf87d1afe0cb1e378d882dce77cb127 (diff) | |
| download | bcm5719-llvm-2362b69dd9e1ad3b5be54780b051bb0f3860853f.tar.gz bcm5719-llvm-2362b69dd9e1ad3b5be54780b051bb0f3860853f.zip | |
[Sparc]: asm-only support for the ldstub instruction.
llvm-svn: 245485
Diffstat (limited to 'llvm/lib/Target/Sparc')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.td | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.td b/llvm/lib/Target/Sparc/SparcInstrInfo.td index 21e9f70e4db..5da4983eab4 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.td +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.td @@ -298,6 +298,17 @@ multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val, def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>; } +// The LDSTUB instruction is supported for asm only. +// It is unlikely that general-purpose code could make use of it. +// CAS is preferred for sparc v9. +def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr), + "ldstub [$addr], $dst", []>; +def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr), + "ldstub [$addr], $dst", []>; +def LDSTUBArr : F3_1_asi<3, 0b011101, (outs IntRegs:$dst), + (ins MEMrr:$addr, i8imm:$asi), + "ldstuba [$addr] $asi, $dst", []>; + // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot. multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> { |
