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| author | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-06-11 19:41:26 +0000 |
|---|---|---|
| committer | Daniel Sanders <daniel.sanders@imgtec.com> | 2015-06-11 19:41:26 +0000 |
| commit | 3e5de88dacfec7ce74b7230be8e392b53d83b050 (patch) | |
| tree | d869b3627be991308573cad1e78fccceb9549d56 /llvm/lib/Target/Sparc/SparcTargetMachine.cpp | |
| parent | c88bf54366f19d849b0b23f1ec6037e10fbc0d05 (diff) | |
| download | bcm5719-llvm-3e5de88dacfec7ce74b7230be8e392b53d83b050.tar.gz bcm5719-llvm-3e5de88dacfec7ce74b7230be8e392b53d83b050.zip | |
Replace string GNU Triples with llvm::Triple in TargetMachine. NFC.
Summary:
For the moment, TargetMachine::getTargetTriple() still returns a StringRef.
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.
Reviewers: rengolin
Reviewed By: rengolin
Subscribers: ted, llvm-commits, rengolin, jholewinski
Differential Revision: http://reviews.llvm.org/D10362
llvm-svn: 239554
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcTargetMachine.cpp | 23 |
1 files changed, 10 insertions, 13 deletions
diff --git a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp index 68f396d4033..725d7f047c4 100644 --- a/llvm/lib/Target/Sparc/SparcTargetMachine.cpp +++ b/llvm/lib/Target/Sparc/SparcTargetMachine.cpp @@ -54,15 +54,15 @@ static std::string computeDataLayout(const Triple &T, bool is64Bit) { /// SparcTargetMachine ctor - Create an ILP32 architecture model /// -SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT, +SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL, bool is64bit) - : LLVMTargetMachine(T, computeDataLayout(Triple(TT), is64bit), TT, CPU, FS, - Options, RM, CM, OL), + : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options, + RM, CM, OL), TLOF(make_unique<SparcELFTargetObjectFile>()), - Subtarget(Triple(TT), CPU, FS, *this, is64bit) { + Subtarget(TT, CPU, FS, *this, is64bit) { initAsmInfo(); } @@ -106,19 +106,16 @@ void SparcPassConfig::addPreEmitPass(){ void SparcV8TargetMachine::anchor() { } -SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, - StringRef TT, StringRef CPU, - StringRef FS, +SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, - Reloc::Model RM, - CodeModel::Model CM, + Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) - : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) { -} + : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} void SparcV9TargetMachine::anchor() { } -SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT, +SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, @@ -127,7 +124,7 @@ SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, StringRef TT, void SparcelTargetMachine::anchor() {} -SparcelTargetMachine::SparcelTargetMachine(const Target &T, StringRef TT, +SparcelTargetMachine::SparcelTargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, |
