summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/Sparc/SparcSubtarget.h
diff options
context:
space:
mode:
authorJames Y Knight <jyknight@google.com>2015-09-10 18:20:45 +0000
committerJames Y Knight <jyknight@google.com>2015-09-10 18:20:45 +0000
commit8a772cfd61e75a46f0f7ace68b0eb8e0510212d9 (patch)
tree642140a8fcbb225df91c89af90e800cd09631f21 /llvm/lib/Target/Sparc/SparcSubtarget.h
parentddb4d9741f985fa5bc86fbaac4607721400f820c (diff)
downloadbcm5719-llvm-8a772cfd61e75a46f0f7ace68b0eb8e0510212d9.tar.gz
bcm5719-llvm-8a772cfd61e75a46f0f7ace68b0eb8e0510212d9.zip
[SPARC] Switch to the Machine Scheduler.
The (mostly-deprecated) SelectionDAG-based ILPListDAGScheduler scheduler was making poor scheduling decisions, causing high register pressure and extraneous register spills. Switching to the newer machine scheduler generates better code -- even without there being a machine model defined for SPARC yet. llvm-svn: 247315
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcSubtarget.h')
-rw-r--r--llvm/lib/Target/Sparc/SparcSubtarget.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.h b/llvm/lib/Target/Sparc/SparcSubtarget.h
index 9d21911d88f..e2fd2f04528 100644
--- a/llvm/lib/Target/Sparc/SparcSubtarget.h
+++ b/llvm/lib/Target/Sparc/SparcSubtarget.h
@@ -60,6 +60,8 @@ public:
return &TSInfo;
}
+ bool enableMachineScheduler() const override;
+
bool isV9() const { return IsV9; }
bool isVIS() const { return IsVIS; }
bool isVIS2() const { return IsVIS2; }
@@ -85,7 +87,6 @@ public:
/// returns adjusted framesize which includes space for register window
/// spills and arguments.
int getAdjustedFrameSize(int stackSize) const;
-
};
} // end namespace llvm
OpenPOWER on IntegriCloud