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| author | Daniel Cederman <cederman@gaisler.com> | 2018-08-27 11:11:47 +0000 |
|---|---|---|
| committer | Daniel Cederman <cederman@gaisler.com> | 2018-08-27 11:11:47 +0000 |
| commit | 2739596063a914f4a1918bde30e72d50fea856c2 (patch) | |
| tree | faff6d3b99db67ab4fa410eebe495b9aa68276c3 /llvm/lib/Target/Sparc/SparcSubtarget.cpp | |
| parent | 9441be6912a8d34245ad928e0d55e4cb3632c4fa (diff) | |
| download | bcm5719-llvm-2739596063a914f4a1918bde30e72d50fea856c2.tar.gz bcm5719-llvm-2739596063a914f4a1918bde30e72d50fea856c2.zip | |
[Sparc] Add support for the cycle counter available in GR740
Summary: The GR740 provides an up cycle counter in the registers ASR22
and ASR23. As these registers can not be read together atomically we only
use the value of ASR23 for llvm.readcyclecounter(). The ASR23 register
holds the 32 LSBs of the up-counter.
Reviewers: jyknight, venkatra
Reviewed By: jyknight
Subscribers: jfb, fedor.sergeev, jrtc27, llvm-commits
Differential Revision: https://reviews.llvm.org/D48638
llvm-svn: 340733
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcSubtarget.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp index 40c5683f849..f3a2049ce38 100644 --- a/llvm/lib/Target/Sparc/SparcSubtarget.cpp +++ b/llvm/lib/Target/Sparc/SparcSubtarget.cpp @@ -47,6 +47,7 @@ SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU, InsertNOPLoad = false; FixAllFDIVSQRT = false; DetectRoundChange = false; + HasLeonCycleCounter = false; // Determine default and user specified characteristics std::string CPUName = CPU; |
