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| author | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-24 22:05:34 +0000 |
|---|---|---|
| committer | Ruchira Sasanka <sasanka@students.uiuc.edu> | 2001-10-24 22:05:34 +0000 |
| commit | 0863c161e9431eec93c6c6e318748019dfb4fed2 (patch) | |
| tree | ac401a0d38ee7aed9edcef1956abc7665a4a26b0 /llvm/lib/Target/Sparc/SparcRegInfo.cpp | |
| parent | f9e623e1f9e4f5df3184772d5bd194664ae06832 (diff) | |
| download | bcm5719-llvm-0863c161e9431eec93c6c6e318748019dfb4fed2.tar.gz bcm5719-llvm-0863c161e9431eec93c6c6e318748019dfb4fed2.zip | |
Fixed load syntax in EmitAssembly
Fixed cpReg2Mem (store) operand oreder in SparcRegInfo.cpp
llvm-svn: 984
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcRegInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcRegInfo.cpp | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/llvm/lib/Target/Sparc/SparcRegInfo.cpp b/llvm/lib/Target/Sparc/SparcRegInfo.cpp index 54cfb3caab5..dfb55176960 100644 --- a/llvm/lib/Target/Sparc/SparcRegInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcRegInfo.cpp @@ -775,8 +775,8 @@ MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg, //--------------------------------------------------------------------------- -// Copy from a register to memory. Register number must be the unified -// register number +// Copy from a register to memory (i.e., Store). Register number must +// be the unified register number //--------------------------------------------------------------------------- @@ -794,24 +794,24 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg, case IntCCRegType: case FloatCCRegType: MI = new MachineInstr(STX, 3); - MI->SetMachineOperand(0, DestPtrReg, false); - MI->SetMachineOperand(1, SrcReg, false); + MI->SetMachineOperand(0, SrcReg, false); + MI->SetMachineOperand(1, DestPtrReg, false); MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset, false); break; case FPSingleRegType: MI = new MachineInstr(ST, 3); - MI->SetMachineOperand(0, DestPtrReg, false); - MI->SetMachineOperand(1, SrcReg, false); + MI->SetMachineOperand(0, SrcReg, false); + MI->SetMachineOperand(1, DestPtrReg, false); MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset, false); break; case FPDoubleRegType: MI = new MachineInstr(STD, 3); - MI->SetMachineOperand(0, DestPtrReg, false); - MI->SetMachineOperand(1, SrcReg, false); + MI->SetMachineOperand(0, SrcReg, false); + MI->SetMachineOperand(1, DestPtrReg, false); MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed, (int64_t) Offset, false); break; @@ -825,7 +825,7 @@ MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg, //--------------------------------------------------------------------------- -// Copy from memory to a reg. Register number must be the unified +// Copy from memory to a reg (i.e., Load) Register number must be the unified // register number //--------------------------------------------------------------------------- |
