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authorRuchira Sasanka <sasanka@students.uiuc.edu>2001-09-15 19:11:31 +0000
committerRuchira Sasanka <sasanka@students.uiuc.edu>2001-09-15 19:11:31 +0000
commit970886e7388c6b90a3fa42f97bd6381b914b34a2 (patch)
tree3b906814fb97c95d9a210dc256919a4d367c805a /llvm/lib/Target/Sparc/SparcInternals.h
parent86b2ad4b7c394a6682182a78dc488055ee7c6912 (diff)
downloadbcm5719-llvm-970886e7388c6b90a3fa42f97bd6381b914b34a2.tar.gz
bcm5719-llvm-970886e7388c6b90a3fa42f97bd6381b914b34a2.zip
modified printing of debug messages
llvm-svn: 593
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInternals.h')
-rw-r--r--llvm/lib/Target/Sparc/SparcInternals.h16
1 files changed, 3 insertions, 13 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInternals.h b/llvm/lib/Target/Sparc/SparcInternals.h
index 43f67d3008a..87e4cd0e983 100644
--- a/llvm/lib/Target/Sparc/SparcInternals.h
+++ b/llvm/lib/Target/Sparc/SparcInternals.h
@@ -945,22 +945,12 @@ class UltraSparcRegInfo : public MachineRegInfo
return res;
}
-
-#if 0
- unsigned getRCIDOfMachineOp (const MachineOperand & Op) const {
-
- unsigned Type = getRegClassIDOfValue( Op.getVRegValue() );
-
- if( Op.getOperandType() == MachineOperand::MO_CCRegister )
- return Type + 2; // because of the order of CC classes
- else return Type;
+ // returns the register tha contains always zero
+ inline unsigned getZeroReg() {
+ return SparcIntRegOrder::g0;
}
-#endif
-
-
-
void colorArgs(const Method *const Meth, LiveRangeInfo& LRI) const;
static void printReg(const LiveRange *const LR) ;
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