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| author | Craig Topper <craig.topper@gmail.com> | 2012-04-20 06:31:50 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-04-20 06:31:50 +0000 |
| commit | abadc660e081d6bebb0f19f441dfb16c3bd08412 (patch) | |
| tree | 2129a714658714d5b59185bc23487851b5483dc7 /llvm/lib/Target/Sparc/SparcInstrInfo.cpp | |
| parent | a7f57e3acaffa2db7d07aca8342cabcc6d390bdd (diff) | |
| download | bcm5719-llvm-abadc660e081d6bebb0f19f441dfb16c3bd08412.tar.gz bcm5719-llvm-abadc660e081d6bebb0f19f441dfb16c3bd08412.zip | |
Convert some uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
llvm-svn: 155186
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index faff468a587..f8674d0bd66 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -303,13 +303,13 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, if (I != MBB.end()) DL = I->getDebugLoc(); // On the order of operands here: think "[FrameIdx + 0] = SrcReg". - if (RC == SP::IntRegsRegisterClass) + if (RC == &SP::IntRegsRegClass) BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); - else if (RC == SP::FPRegsRegisterClass) + else if (RC == &SP::FPRegsRegClass) BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); - else if (RC == SP::DFPRegsRegisterClass) + else if (RC == &SP::DFPRegsRegClass) BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0) .addReg(SrcReg, getKillRegState(isKill)); else @@ -324,11 +324,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL; if (I != MBB.end()) DL = I->getDebugLoc(); - if (RC == SP::IntRegsRegisterClass) + if (RC == &SP::IntRegsRegClass) BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); - else if (RC == SP::FPRegsRegisterClass) + else if (RC == &SP::FPRegsRegClass) BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); - else if (RC == SP::DFPRegsRegisterClass) + else if (RC == &SP::DFPRegsRegClass) BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0); else llvm_unreachable("Can't load this register from stack slot"); |
