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author | Dan Gohman <gohman@apple.com> | 2008-07-07 23:14:23 +0000 |
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committer | Dan Gohman <gohman@apple.com> | 2008-07-07 23:14:23 +0000 |
commit | 3b46030375b309ac6e198664bbbf859884318084 (patch) | |
tree | 384b02de07f0f190d5753652f676f6c9a9a7d00c /llvm/lib/Target/Sparc/SparcInstrInfo.cpp | |
parent | 7f8b6d5f8034a78638f9e82e42b6e647bed7106e (diff) | |
download | bcm5719-llvm-3b46030375b309ac6e198664bbbf859884318084.tar.gz bcm5719-llvm-3b46030375b309ac6e198664bbbf859884318084.zip |
Pool-allocation for MachineInstrs, MachineBasicBlocks, and
MachineMemOperands. The pools are owned by MachineFunctions.
This drastically reduces the number of calls to malloc/free made
during the "Emit" phase of scheduling, as well as later phases
in CodeGen. Combined with other changes, this speeds up the
"instruction selection" phase of CodeGen by 10% in some cases.
llvm-svn: 53212
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstrInfo.cpp')
-rw-r--r-- | llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index 67df87b5f07..2476f4cc5ef 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -162,7 +162,7 @@ void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, Opc = SP::STDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(get(Opc)); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc)); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isRegister()) @@ -206,7 +206,7 @@ void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, Opc = SP::LDDFri; else assert(0 && "Can't load this register"); - MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg); + MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg); for (unsigned i = 0, e = Addr.size(); i != e; ++i) { MachineOperand &MO = Addr[i]; if (MO.isReg()) @@ -236,10 +236,10 @@ MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&& MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) { if (OpNum == 0) // COPY -> STORE - NewMI = BuildMI(get(SP::STri)).addFrameIndex(FI).addImm(0) + NewMI = BuildMI(MF, get(SP::STri)).addFrameIndex(FI).addImm(0) .addReg(MI->getOperand(2).getReg()); else // COPY -> LOAD - NewMI = BuildMI(get(SP::LDri), MI->getOperand(0).getReg()) + NewMI = BuildMI(MF, get(SP::LDri), MI->getOperand(0).getReg()) .addFrameIndex(FI).addImm(0); } break; @@ -250,12 +250,12 @@ MachineInstr *SparcInstrInfo::foldMemoryOperand(MachineFunction &MF, if (OpNum == 0) { // COPY -> STORE unsigned SrcReg = MI->getOperand(1).getReg(); bool isKill = MI->getOperand(1).isKill(); - NewMI = BuildMI(get(isFloat ? SP::STFri : SP::STDFri)) + NewMI = BuildMI(MF, get(isFloat ? SP::STFri : SP::STDFri)) .addFrameIndex(FI).addImm(0).addReg(SrcReg, false, false, isKill); } else { // COPY -> LOAD unsigned DstReg = MI->getOperand(0).getReg(); bool isDead = MI->getOperand(0).isDead(); - NewMI = BuildMI(get(isFloat ? SP::LDFri : SP::LDDFri)) + NewMI = BuildMI(MF, get(isFloat ? SP::LDFri : SP::LDDFri)) .addReg(DstReg, true, false, false, isDead).addFrameIndex(FI).addImm(0); } break; |