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| author | James Y Knight <jyknight@google.com> | 2016-05-23 20:33:00 +0000 |
|---|---|---|
| committer | James Y Knight <jyknight@google.com> | 2016-05-23 20:33:00 +0000 |
| commit | fdcc727da6fa4f9fd9d572d7d5d3a22019fdae93 (patch) | |
| tree | 993898787af586e27b62b0d98fd8171e5ee9b6b4 /llvm/lib/Target/Sparc/SparcInstr64Bit.td | |
| parent | 2280f9325e6993df3d858300b9ab6901a6b78ba4 (diff) | |
| download | bcm5719-llvm-fdcc727da6fa4f9fd9d572d7d5d3a22019fdae93.tar.gz bcm5719-llvm-fdcc727da6fa4f9fd9d572d7d5d3a22019fdae93.zip | |
[SPARC] Fix 8 and 16-bit atomic load and store.
They were accidentally using the 32-bit load/store instruction for
8/16-bit operations, due to incorrect patterns
(8/16-bit cmpxchg and atomicrmw will be fixed in subsequent changes)
llvm-svn: 270486
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcInstr64Bit.td')
| -rw-r--r-- | llvm/lib/Target/Sparc/SparcInstr64Bit.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/Sparc/SparcInstr64Bit.td b/llvm/lib/Target/Sparc/SparcInstr64Bit.td index 299f00e5247..f6518c936eb 100644 --- a/llvm/lib/Target/Sparc/SparcInstr64Bit.td +++ b/llvm/lib/Target/Sparc/SparcInstr64Bit.td @@ -492,7 +492,7 @@ let Predicates = [Is64Bit], Constraints = "$swap = $rd", asi = 0b10000000 in { I64Regs:$swap), "casx [$rs1], $rs2, $rd", [(set i64:$rd, - (atomic_cmp_swap i64:$rs1, i64:$rs2, i64:$swap))]>; + (atomic_cmp_swap_64 i64:$rs1, i64:$rs2, i64:$swap))]>; } // Predicates = [Is64Bit], Constraints = ... @@ -501,12 +501,12 @@ let Predicates = [Is64Bit] in { def : Pat<(atomic_fence imm, imm), (MEMBARi 0xf)>; // atomic_load_64 addr -> load addr -def : Pat<(i64 (atomic_load ADDRrr:$src)), (LDXrr ADDRrr:$src)>; -def : Pat<(i64 (atomic_load ADDRri:$src)), (LDXri ADDRri:$src)>; +def : Pat<(i64 (atomic_load_64 ADDRrr:$src)), (LDXrr ADDRrr:$src)>; +def : Pat<(i64 (atomic_load_64 ADDRri:$src)), (LDXri ADDRri:$src)>; // atomic_store_64 val, addr -> store val, addr -def : Pat<(atomic_store ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>; -def : Pat<(atomic_store ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>; +def : Pat<(atomic_store_64 ADDRrr:$dst, i64:$val), (STXrr ADDRrr:$dst, $val)>; +def : Pat<(atomic_store_64 ADDRri:$dst, i64:$val), (STXri ADDRri:$dst, $val)>; } // Predicates = [Is64Bit] |
