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authorVenkatraman Govindaraju <venkatra@cs.wisc.edu>2014-03-02 09:46:56 +0000
committerVenkatraman Govindaraju <venkatra@cs.wisc.edu>2014-03-02 09:46:56 +0000
commitb745e67a64e617d4f3f3e804014a4ef9775463b8 (patch)
tree8d634663f06c9b09b39882ac58acec441d2872fd /llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
parent5de228b28716ff0bb2f29b45e96334b535457fe7 (diff)
downloadbcm5719-llvm-b745e67a64e617d4f3f3e804014a4ef9775463b8.tar.gz
bcm5719-llvm-b745e67a64e617d4f3f3e804014a4ef9775463b8.zip
[SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
llvm-svn: 202628
Diffstat (limited to 'llvm/lib/Target/Sparc/SparcCodeEmitter.cpp')
-rw-r--r--llvm/lib/Target/Sparc/SparcCodeEmitter.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp b/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
index 6b5e4bf0f5b..97bacf2d319 100644
--- a/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
+++ b/llvm/lib/Target/Sparc/SparcCodeEmitter.cpp
@@ -78,6 +78,8 @@ private:
unsigned) const;
unsigned getBranchPredTargetOpValue(const MachineInstr &MI,
unsigned) const;
+ unsigned getBranchOnRegTargetOpValue(const MachineInstr &MI,
+ unsigned) const;
void emitWord(unsigned Word);
@@ -206,6 +208,12 @@ unsigned SparcCodeEmitter::getBranchPredTargetOpValue(const MachineInstr &MI,
return getMachineOpValue(MI, MO);
}
+unsigned SparcCodeEmitter::getBranchOnRegTargetOpValue(const MachineInstr &MI,
+ unsigned opIdx) const {
+ const MachineOperand MO = MI.getOperand(opIdx);
+ return getMachineOpValue(MI, MO);
+}
+
unsigned SparcCodeEmitter::getRelocation(const MachineInstr &MI,
const MachineOperand &MO) const {
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