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| author | Alex Bradbury <asb@lowrisc.org> | 2018-10-03 11:04:59 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-10-03 11:04:59 +0000 |
| commit | a9ac5994b1ec3b17639c755117c5c56fd40e3e8a (patch) | |
| tree | f92ae078cb211fafb3964e5110d078c0756351de /llvm/lib/Target/RISCV | |
| parent | 11a1423348551058fb5683fee643c3b19094de54 (diff) | |
| download | bcm5719-llvm-a9ac5994b1ec3b17639c755117c5c56fd40e3e8a.tar.gz bcm5719-llvm-a9ac5994b1ec3b17639c755117c5c56fd40e3e8a.zip | |
[RISCV] Gate simm32 materialisation pattern and SW pattern on IsRV32
These patterns are not correct for RV64.
llvm-svn: 343677
Diffstat (limited to 'llvm/lib/Target/RISCV')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfo.td | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index efbcd771c8e..24665bd4acc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -625,7 +625,8 @@ def IsOrAdd: PatFrag<(ops node:$A, node:$B), (or node:$A, node:$B), [{ def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>; def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>; -def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>; +def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>, + Requires<[IsRV32]>; /// Simple arithmetic operations @@ -808,7 +809,7 @@ multiclass StPat<PatFrag StoreOp, RVInst Inst, RegisterClass StTy> { defm : StPat<truncstorei8, SB, GPR>; defm : StPat<truncstorei16, SH, GPR>; -defm : StPat<store, SW, GPR>; +defm : StPat<store, SW, GPR>, Requires<[IsRV32]>; /// Fences |
