diff options
| author | Alex Bradbury <asb@lowrisc.org> | 2018-06-20 14:03:02 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-06-20 14:03:02 +0000 |
| commit | 79d2b50ca81fae77362bcd423bcd795c8d0498d8 (patch) | |
| tree | 286f696f6ccadf22ea243e91d9999fd8c064336e /llvm/lib/Target/RISCV | |
| parent | 027fd8068f055962111aaff64477892fd44f61e5 (diff) | |
| download | bcm5719-llvm-79d2b50ca81fae77362bcd423bcd795c8d0498d8.tar.gz bcm5719-llvm-79d2b50ca81fae77362bcd423bcd795c8d0498d8.zip | |
[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}
These are produced by GCC and supported by GAS, but not currently contained in
the pseudoinstruction listing in the RISC-V ISA manual.
llvm-svn: 335127
Diffstat (limited to 'llvm/lib/Target/RISCV')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 7 | ||||
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td index b308cb990a0..06b834d55ad 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td @@ -185,6 +185,13 @@ let Predicates = [HasStdExtD] in { def : InstAlias<"fmv.d $rd, $rs", (FSGNJ_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>; + +// fgt.d/fge.d are recognised by the GNU assembler but the canonical +// flt.d/fle.d forms will always be printed. Therefore, set a zero weight. +def : InstAlias<"fgt.d $rd, $rs, $rt", + (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; +def : InstAlias<"fge.d $rd, $rs, $rt", + (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>; } // Predicates = [HasStdExtD] //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td index 6121dea277c..12b1d9a857f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td @@ -200,6 +200,13 @@ def : InstAlias<"fmv.s $rd, $rs", (FSGNJ_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>; +// fgt.s/fge.s are recognised by the GNU assembler but the canonical +// flt.s/fle.s forms will always be printed. Therefore, set a zero weight. +def : InstAlias<"fgt.s $rd, $rs, $rt", + (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; +def : InstAlias<"fge.s $rd, $rs, $rt", + (FLE_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>; + // The following csr instructions actually alias instructions from the base ISA. // However, it only makes sense to support them when the F extension is enabled. // CSR Addresses: 0x003 == fcsr, 0x002 == frm, 0x001 == fflags |
