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authorZakk Chen <zakk.chen@sifive.com>2019-11-28 18:00:54 -0800
committerHans Wennborg <hans@chromium.org>2020-01-27 19:07:09 +0100
commit72882ca30d87bd7ea85d8099e8b9d2244749b71e (patch)
tree08dc97948df36efcacf5742a1152fce2504eb57b /llvm/lib/Target/RISCV
parent4d342b7d8e9bc6f40001011b51b5ad812535c4a6 (diff)
downloadbcm5719-llvm-72882ca30d87bd7ea85d8099e8b9d2244749b71e.tar.gz
bcm5719-llvm-72882ca30d87bd7ea85d8099e8b9d2244749b71e.zip
[RISCV] Support ABI checking with per function target-features
1. if users don't specific -mattr, the default target-feature come from IR attribute. 2. fixed bug and re-land this patch Reviewers: lenary, asb Reviewed By: lenary Tags: #llvm Differential Revision: https://reviews.llvm.org/D70837 (cherry picked from commit 0cb274de397a193fb37c60653b336d48a3a4f1bd)
Diffstat (limited to 'llvm/lib/Target/RISCV')
-rw-r--r--llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp13
-rw-r--r--llvm/lib/Target/RISCV/RISCVISelLowering.cpp14
-rw-r--r--llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp11
3 files changed, 28 insertions, 10 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index cfd83e4189f..c7efdf42a7c 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -194,6 +194,19 @@ public:
Parser.addAliasForDirective(".word", ".4byte");
Parser.addAliasForDirective(".dword", ".8byte");
setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
+
+ auto ABIName = StringRef(Options.ABIName);
+ if (ABIName.endswith("f") &&
+ !getSTI().getFeatureBits()[RISCV::FeatureStdExtF]) {
+ errs() << "Hard-float 'f' ABI can't be used for a target that "
+ "doesn't support the F instruction set extension (ignoring "
+ "target-abi)\n";
+ } else if (ABIName.endswith("d") &&
+ !getSTI().getFeatureBits()[RISCV::FeatureStdExtD]) {
+ errs() << "Hard-float 'd' ABI can't be used for a target that "
+ "doesn't support the D instruction set extension (ignoring "
+ "target-abi)\n";
+ }
}
};
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0b1fd382366..5a2cffbc824 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -51,6 +51,20 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
RISCVABI::ABI ABI = Subtarget.getTargetABI();
assert(ABI != RISCVABI::ABI_Unknown && "Improperly initialised target ABI");
+ if ((ABI == RISCVABI::ABI_ILP32F || ABI == RISCVABI::ABI_LP64F) &&
+ !Subtarget.hasStdExtF()) {
+ errs() << "Hard-float 'f' ABI can't be used for a target that "
+ "doesn't support the F instruction set extension (ignoring "
+ "target-abi)\n";
+ ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
+ } else if ((ABI == RISCVABI::ABI_ILP32D || ABI == RISCVABI::ABI_LP64D) &&
+ !Subtarget.hasStdExtD()) {
+ errs() << "Hard-float 'd' ABI can't be used for a target that "
+ "doesn't support the D instruction set extension (ignoring "
+ "target-abi)\n";
+ ABI = Subtarget.is64Bit() ? RISCVABI::ABI_LP64 : RISCVABI::ABI_ILP32;
+ }
+
switch (ABI) {
default:
report_fatal_error("Don't know how to lower this ABI");
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
index da87722632e..43b1f8b80c5 100644
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp
@@ -28,17 +28,8 @@ ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
errs() << "64-bit ABIs are not supported for 32-bit targets (ignoring "
"target-abi)\n";
TargetABI = ABI_Unknown;
- } else if (ABIName.endswith("f") && !FeatureBits[RISCV::FeatureStdExtF]) {
- errs() << "Hard-float 'f' ABI can't be used for a target that "
- "doesn't support the F instruction set extension (ignoring "
- "target-abi)\n";
- TargetABI = ABI_Unknown;
- } else if (ABIName.endswith("d") && !FeatureBits[RISCV::FeatureStdExtD]) {
- errs() << "Hard-float 'd' ABI can't be used for a target that "
- "doesn't support the D instruction set extension (ignoring "
- "target-abi)\n";
- TargetABI = ABI_Unknown;
} else if (IsRV32E && TargetABI != ABI_ILP32E && TargetABI != ABI_Unknown) {
+ // TODO: move this checking to RISCVTargetLowering and RISCVAsmParser
errs()
<< "Only the ilp32e ABI is supported for RV32E (ignoring target-abi)\n";
TargetABI = ABI_Unknown;
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