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| author | Ana Pazos <apazos@codeaurora.org> | 2018-08-09 20:51:53 +0000 |
|---|---|---|
| committer | Ana Pazos <apazos@codeaurora.org> | 2018-08-09 20:51:53 +0000 |
| commit | 10de234905ea9dd310cb3047c7b9aa6c460c5653 (patch) | |
| tree | 60d3b609304482abae80224092a630cc09f4d6fd /llvm/lib/Target/RISCV | |
| parent | 03406c50faa9d8f8a731551318644db2831bfa01 (diff) | |
| download | bcm5719-llvm-10de234905ea9dd310cb3047c7b9aa6c460c5653.tar.gz bcm5719-llvm-10de234905ea9dd310cb3047c7b9aa6c460c5653.zip | |
[RISC-V] Fixed alias for addi x2, x2, 0
A missing check for non-zero immediate in MCOperandPredicate
caused c.addi16sp sp, 0 to be selected which is not a valid
instruction.
llvm-svn: 339381
Diffstat (limited to 'llvm/lib/Target/RISCV')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index 5d1c62c0b65..eae94419772 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -187,7 +187,7 @@ def simm10_lsb0000nonzero : Operand<XLenVT>, int64_t Imm; if (!MCOp.evaluateAsConstantImm(Imm)) return false; - return isShiftedInt<6, 4>(Imm); + return isShiftedInt<6, 4>(Imm) && (Imm != 0); }]; } |
