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| author | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:46:23 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-12-07 10:46:23 +0000 |
| commit | 7bc2a95bb98a5e589cf2a098f2b6c4eae3e4c072 (patch) | |
| tree | e812ff14e80035228b8ad1a0855c39546072921b /llvm/lib/Target/RISCV/RISCVSubtarget.h | |
| parent | a8a83d150f489733353b3bff0891248f59a0794c (diff) | |
| download | bcm5719-llvm-7bc2a95bb98a5e589cf2a098f2b6c4eae3e4c072.tar.gz bcm5719-llvm-7bc2a95bb98a5e589cf2a098f2b6c4eae3e4c072.zip | |
[RISCV] MC layer support for the standard RV32D instruction set extension
As the FPR32 and FPR64 registers have the same names, use
validateTargetOperandClass in RISCVAsmParser to coerce a parsed FPR32 to an
FPR64 when necessary. The rest of this patch is very similar to the RV32F
patch.
Differential Revision: https://reviews.llvm.org/D39895
llvm-svn: 320023
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVSubtarget.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index 82edef65e11..7db49456ebc 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -33,6 +33,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { bool HasStdExtM = false; bool HasStdExtA = false; bool HasStdExtF = false; + bool HasStdExtD = false; bool HasRV64 = false; unsigned XLen = 32; MVT XLenVT = MVT::i32; @@ -72,6 +73,7 @@ public: bool hasStdExtM() const { return HasStdExtM; } bool hasStdExtA() const { return HasStdExtA; } bool hasStdExtF() const { return HasStdExtF; } + bool hasStdExtD() const { return HasStdExtD; } bool is64Bit() const { return HasRV64; } MVT getXLenVT() const { return XLenVT; } unsigned getXLen() const { return XLen; } |
