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| author | Luis Marques <luismarques@lowrisc.org> | 2019-09-17 11:15:35 +0000 |
|---|---|---|
| committer | Luis Marques <luismarques@lowrisc.org> | 2019-09-17 11:15:35 +0000 |
| commit | 3d0fbafd0bce43bb9106230a45d1130f7a40e5ec (patch) | |
| tree | e71d5a01eeebf585596a126cd834fddab0c2c784 /llvm/lib/Target/RISCV/RISCVSubtarget.h | |
| parent | 3ab9e8b81858cdcf4f381b4238315cb1d434e984 (diff) | |
| download | bcm5719-llvm-3d0fbafd0bce43bb9106230a45d1130f7a40e5ec.tar.gz bcm5719-llvm-3d0fbafd0bce43bb9106230a45d1130f7a40e5ec.zip | |
[RISCV] Switch to the Machine Scheduler
Most of the test changes are trivial instruction reorderings and differing
register allocations, without any obvious performance impact.
Differential Revision: https://reviews.llvm.org/D66973
llvm-svn: 372106
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVSubtarget.h')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVSubtarget.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h index fa19252f1f1..7d0373a5253 100644 --- a/llvm/lib/Target/RISCV/RISCVSubtarget.h +++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h @@ -80,6 +80,7 @@ public: const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { return &TSInfo; } + bool enableMachineScheduler() const override { return true; } bool hasStdExtM() const { return HasStdExtM; } bool hasStdExtA() const { return HasStdExtA; } bool hasStdExtF() const { return HasStdExtF; } |
