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authorDaniel Sanders <daniel_l_sanders@apple.com>2019-08-20 22:53:24 +0000
committerDaniel Sanders <daniel_l_sanders@apple.com>2019-08-20 22:53:24 +0000
commita16bd4f9f25e6fa489f070743147ba5e7d6e58cf (patch)
treec1d7eb811270ecd112b433e415ea861e7993d4b0 /llvm/lib/Target/RISCV/RISCVSubtarget.cpp
parent2863721f0582b304d37c8b37b92574d246598b18 (diff)
downloadbcm5719-llvm-a16bd4f9f25e6fa489f070743147ba5e7d6e58cf.tar.gz
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[RISCV GlobalISel] Adding initial GlobalISel infrastructure
Summary: Add an initial GlobalISel skeleton for RISCV. It can only run ir translator for `ret void`. Patch by Andrew Wei Reviewers: asb, sabuasal, apazos, lenary, simoncook, lewis-revill, edward-jones, rogfer01, xiangzhai, rovka, Petar.Avramovic, mgorny, dsanders Reviewed By: dsanders Subscribers: pzheng, s.egerton, dsanders, hiraditya, rbar, johnrusso, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, psnobl, benna, Jim, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D65219 llvm-svn: 369467
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVSubtarget.cpp')
-rw-r--r--llvm/lib/Target/RISCV/RISCVSubtarget.cpp30
1 files changed, 29 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 6902ed75d85..5673f2205a6 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -12,7 +12,11 @@
#include "RISCVSubtarget.h"
#include "RISCV.h"
+#include "RISCVCallLowering.h"
#include "RISCVFrameLowering.h"
+#include "RISCVLegalizerInfo.h"
+#include "RISCVRegisterBankInfo.h"
+#include "RISCVTargetMachine.h"
#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
@@ -47,4 +51,28 @@ RISCVSubtarget::RISCVSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
StringRef ABIName, const TargetMachine &TM)
: RISCVGenSubtargetInfo(TT, CPU, FS),
FrameLowering(initializeSubtargetDependencies(TT, CPU, FS, ABIName)),
- InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {}
+ InstrInfo(), RegInfo(getHwMode()), TLInfo(TM, *this) {
+ CallLoweringInfo.reset(new RISCVCallLowering(*getTargetLowering()));
+ Legalizer.reset(new RISCVLegalizerInfo(*this));
+
+ auto *RBI = new RISCVRegisterBankInfo(*getRegisterInfo());
+ RegBankInfo.reset(RBI);
+ InstSelector.reset(createRISCVInstructionSelector(
+ *static_cast<const RISCVTargetMachine *>(&TM), *this, *RBI));
+}
+
+const CallLowering *RISCVSubtarget::getCallLowering() const {
+ return CallLoweringInfo.get();
+}
+
+InstructionSelector *RISCVSubtarget::getInstructionSelector() const {
+ return InstSelector.get();
+}
+
+const LegalizerInfo *RISCVSubtarget::getLegalizerInfo() const {
+ return Legalizer.get();
+}
+
+const RegisterBankInfo *RISCVSubtarget::getRegBankInfo() const {
+ return RegBankInfo.get();
+}
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