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| author | Alex Bradbury <asb@lowrisc.org> | 2018-04-12 05:42:42 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2018-04-12 05:42:42 +0000 |
| commit | 5d0dfa5e0e758fb075b70c4686e46abf45f3c3ba (patch) | |
| tree | 9159564127fd554c740c3a982bd9b18a0dc8da01 /llvm/lib/Target/RISCV/RISCVISelLowering.cpp | |
| parent | dfaa021e990238902823882858b873d96eacb4da (diff) | |
| download | bcm5719-llvm-5d0dfa5e0e758fb075b70c4686e46abf45f3c3ba.tar.gz bcm5719-llvm-5d0dfa5e0e758fb075b70c4686e46abf45f3c3ba.zip | |
[RISCV] Add codegen support for RV32D floating point arithmetic operations
llvm-svn: 329874
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVISelLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3457ed599df..8b006d2d321 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -121,8 +121,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::BR_CC, MVT::f32, Expand); } - if (Subtarget.hasStdExtD()) + if (Subtarget.hasStdExtD()) { + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand); + } setOperationAction(ISD::GlobalAddress, XLenVT, Custom); setOperationAction(ISD::BlockAddress, XLenVT, Custom); |
