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authorShiva Chen <shiva0217@gmail.com>2019-09-13 02:50:13 +0000
committerShiva Chen <shiva0217@gmail.com>2019-09-13 02:50:13 +0000
commiteaa230fe3c868beeaea70b7621acc9bfaf126d04 (patch)
tree52c4ca3811ac0c207dfa2b96063e689ecc88a0aa /llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
parent49c4e58b75ecec8dce75dd13c61aaeb30e14b531 (diff)
downloadbcm5719-llvm-eaa230fe3c868beeaea70b7621acc9bfaf126d04.tar.gz
bcm5719-llvm-eaa230fe3c868beeaea70b7621acc9bfaf126d04.zip
[RISCV] Support stack offset exceed 32-bit for RV64
Differential Revision: https://reviews.llvm.org/D61884 llvm-svn: 371806
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVFrameLowering.cpp')
-rw-r--r--llvm/lib/Target/RISCV/RISCVFrameLowering.cpp6
1 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index ad19741a427..7d48634f206 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -74,7 +74,7 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
.addReg(SrcReg)
.addImm(Val)
.setMIFlag(Flag);
- } else if (isInt<32>(Val)) {
+ } else {
unsigned Opc = RISCV::ADD;
bool isSub = Val < 0;
if (isSub) {
@@ -83,13 +83,11 @@ void RISCVFrameLowering::adjustReg(MachineBasicBlock &MBB,
}
Register ScratchReg = MRI.createVirtualRegister(&RISCV::GPRRegClass);
- TII->movImm32(MBB, MBBI, DL, ScratchReg, Val, Flag);
+ TII->movImm(MBB, MBBI, DL, ScratchReg, Val, Flag);
BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
.addReg(SrcReg)
.addReg(ScratchReg, RegState::Kill)
.setMIFlag(Flag);
- } else {
- report_fatal_error("adjustReg cannot yet handle adjustments >32 bits");
}
}
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