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| author | Alex Bradbury <asb@lowrisc.org> | 2017-09-17 14:36:28 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2017-09-17 14:36:28 +0000 |
| commit | 8ab4a9696a7753c546caff4fd21826ea72370648 (patch) | |
| tree | 7e51c89b9e72b3376bb4b34e300f45c789f55505 /llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | |
| parent | 6758ecb98cf6a1e2d99f6a53cffe7d4848371cbc (diff) | |
| download | bcm5719-llvm-8ab4a9696a7753c546caff4fd21826ea72370648.tar.gz bcm5719-llvm-8ab4a9696a7753c546caff4fd21826ea72370648.zip | |
[RISCV] Add support for disassembly
This Disassembly support allows for 'round-trip' testing, and rv32i-valid.s
has been updated appropriately.
Differential Revision: https://reviews.llvm.org/D23567
llvm-svn: 313486
Diffstat (limited to 'llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp index 0f68dd7aa05..2b35eab577b 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -29,6 +29,9 @@ #define GET_REGINFO_MC_DESC #include "RISCVGenRegisterInfo.inc" +#define GET_SUBTARGETINFO_MC_DESC +#include "RISCVGenSubtargetInfo.inc" + using namespace llvm; static MCInstrInfo *createRISCVMCInstrInfo() { @@ -64,5 +67,6 @@ extern "C" void LLVMInitializeRISCVTargetMC() { TargetRegistry::RegisterMCAsmBackend(*T, createRISCVAsmBackend); TargetRegistry::RegisterMCCodeEmitter(*T, createRISCVMCCodeEmitter); TargetRegistry::RegisterMCInstPrinter(*T, createRISCVMCInstPrinter); + TargetRegistry::RegisterMCSubtargetInfo(*T, createRISCVMCSubtargetInfoImpl); } } |
