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| author | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2019-01-24 23:44:28 +0000 |
|---|---|---|
| committer | Nemanja Ivanovic <nemanja.i.ibm@gmail.com> | 2019-01-24 23:44:28 +0000 |
| commit | b9b75de0aebce6fec139ab52ab6bf4bca2d41ee9 (patch) | |
| tree | 0b61ccfdb5b115a65bc89d394c1516c51ee3f46b /llvm/lib/Target/RISCV/AsmParser | |
| parent | 6bab7ab11e75f675f561162f40c9b28525b4e473 (diff) | |
| download | bcm5719-llvm-b9b75de0aebce6fec139ab52ab6bf4bca2d41ee9.tar.gz bcm5719-llvm-b9b75de0aebce6fec139ab52ab6bf4bca2d41ee9.zip | |
[PowerPC] Exploit store instructions that store a single vector element
This patch exploits the instructions that store a single element from a vector
to preform a (store (extract_elt)). We already have code that does this with
ISA 3.0 instructions that were added to handle i8/i16 types. However, we had
never exploited the existing ones that handle f32/f64/i32/i64 types.
Differential revision: https://reviews.llvm.org/D56175
llvm-svn: 352131
Diffstat (limited to 'llvm/lib/Target/RISCV/AsmParser')
0 files changed, 0 insertions, 0 deletions
