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authorAlex Bradbury <asb@lowrisc.org>2018-11-28 16:39:14 +0000
committerAlex Bradbury <asb@lowrisc.org>2018-11-28 16:39:14 +0000
commit893e5bc77484e93d7219eb5aef3534cbe6a14bb5 (patch)
treef03fee86fe12d19d6e87f481c6fe03842585d687 /llvm/lib/Target/RISCV/AsmParser
parent8d63aed45941eb40ee30cf80584d6fd024d56b53 (diff)
downloadbcm5719-llvm-893e5bc77484e93d7219eb5aef3534cbe6a14bb5.tar.gz
bcm5719-llvm-893e5bc77484e93d7219eb5aef3534cbe6a14bb5.zip
[RISCV] Support .option push and .option pop
This adds support in the RISCVAsmParser the storing of Subtarget feature bits to a stack so that they can be pushed/popped to enable/disable multiple features at once. Differential Revision: https://reviews.llvm.org/D46424 Patch by Lewis Revill. llvm-svn: 347774
Diffstat (limited to 'llvm/lib/Target/RISCV/AsmParser')
-rw-r--r--llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp47
1 files changed, 46 insertions, 1 deletions
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 331eb2b361c..4e70ea402d8 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -14,6 +14,7 @@
#include "Utils/RISCVBaseInfo.h"
#include "Utils/RISCVMatInt.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
#include "llvm/MC/MCAssembler.h"
#include "llvm/MC/MCContext.h"
@@ -42,6 +43,8 @@ namespace {
struct RISCVOperand;
class RISCVAsmParser : public MCTargetAsmParser {
+ SmallVector<FeatureBitset, 4> FeatureBitStack;
+
SMLoc getLoc() const { return getParser().getTok().getLoc(); }
bool isRV64() const { return getSTI().hasFeature(RISCV::Feature64Bit); }
@@ -118,6 +121,20 @@ class RISCVAsmParser : public MCTargetAsmParser {
}
}
+ void pushFeatureBits() {
+ FeatureBitStack.push_back(getSTI().getFeatureBits());
+ }
+
+ bool popFeatureBits() {
+ if (FeatureBitStack.empty())
+ return true;
+
+ FeatureBitset FeatureBits = FeatureBitStack.pop_back_val();
+ copySTI().setFeatureBits(FeatureBits);
+ setAvailableFeatures(ComputeAvailableFeatures(FeatureBits));
+
+ return false;
+ }
public:
enum RISCVMatchResultTy {
Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
@@ -1285,6 +1302,33 @@ bool RISCVAsmParser::parseDirectiveOption() {
StringRef Option = Tok.getIdentifier();
+ if (Option == "push") {
+ getTargetStreamer().emitDirectiveOptionPush();
+
+ Parser.Lex();
+ if (Parser.getTok().isNot(AsmToken::EndOfStatement))
+ return Error(Parser.getTok().getLoc(),
+ "unexpected token, expected end of statement");
+
+ pushFeatureBits();
+ return false;
+ }
+
+ if (Option == "pop") {
+ SMLoc StartLoc = Parser.getTok().getLoc();
+ getTargetStreamer().emitDirectiveOptionPop();
+
+ Parser.Lex();
+ if (Parser.getTok().isNot(AsmToken::EndOfStatement))
+ return Error(Parser.getTok().getLoc(),
+ "unexpected token, expected end of statement");
+
+ if (popFeatureBits())
+ return Error(StartLoc, ".option pop with no .option push");
+
+ return false;
+ }
+
if (Option == "rvc") {
getTargetStreamer().emitDirectiveOptionRVC();
@@ -1335,7 +1379,8 @@ bool RISCVAsmParser::parseDirectiveOption() {
// Unknown option.
Warning(Parser.getTok().getLoc(),
- "unknown option, expected 'rvc', 'norvc', 'relax' or 'norelax'");
+ "unknown option, expected 'push', 'pop', 'rvc', 'norvc', 'relax' or "
+ "'norelax'");
Parser.eatToEndOfStatement();
return false;
}
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