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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 20:59:25 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-01-07 20:59:25 +0000 |
| commit | 45c0b3a8828179519a66d98f0eb20170bd009744 (patch) | |
| tree | 338887688be7dc13eac18b976da27929e220a971 /llvm/lib/Target/R600/SILowerControlFlow.cpp | |
| parent | 842b4aecf87856a90cfcb4e3fa14fdb1dff32fcc (diff) | |
| download | bcm5719-llvm-45c0b3a8828179519a66d98f0eb20170bd009744.tar.gz bcm5719-llvm-45c0b3a8828179519a66d98f0eb20170bd009744.zip | |
R600/SI: Remove VReg_32 register class
Use VGPR_32 register class instead. These two register classes were
identical and having separate classes was causing
SIInstrInfo::isLegalOperands() to be overly conservative in some cases.
This change is necessary to prevent future paches from missing a folding
opportunity in fneg-fabs.ll.
llvm-svn: 225382
Diffstat (limited to 'llvm/lib/Target/R600/SILowerControlFlow.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SILowerControlFlow.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SILowerControlFlow.cpp b/llvm/lib/Target/R600/SILowerControlFlow.cpp index aaf91ea8281..90174d7b30a 100644 --- a/llvm/lib/Target/R600/SILowerControlFlow.cpp +++ b/llvm/lib/Target/R600/SILowerControlFlow.cpp @@ -340,7 +340,7 @@ void SILowerControlFlowPass::LoadM0(MachineInstr &MI, MachineInstr *MovRel) { } else { assert(AMDGPU::SReg_64RegClass.contains(Save)); - assert(AMDGPU::VReg_32RegClass.contains(Idx)); + assert(AMDGPU::VGPR_32RegClass.contains(Idx)); // Save the EXEC mask BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_MOV_B64), Save) |
