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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:20 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:20 +0000 |
| commit | 82bef57f2047a96f301130fafc8cb3d38e6238c5 (patch) | |
| tree | dee4f37f1c75264044807e7f4ecf0fa2cd8f6432 /llvm/lib/Target/R600/SIInsertWaits.cpp | |
| parent | b03edeca6731856fe43e8aca739957c482a6257c (diff) | |
| download | bcm5719-llvm-82bef57f2047a96f301130fafc8cb3d38e6238c5.tar.gz bcm5719-llvm-82bef57f2047a96f301130fafc8cb3d38e6238c5.zip | |
R600/SI: Fix incorrect encoding of DS_WRITE_B32 instructions
The SIInsertWaits pass was overwriting the first operand (gds bit) of
DS_WRITE_B32 with the second operand (value to write). This meant that
any time the value to write was stored in an odd number VGPR, the gds
bit would be set causing the instruction to write to GDS instead of LDS.
llvm-svn: 188522
Diffstat (limited to 'llvm/lib/Target/R600/SIInsertWaits.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIInsertWaits.cpp | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SIInsertWaits.cpp b/llvm/lib/Target/R600/SIInsertWaits.cpp index ba202e3cbf6..c477be5a890 100644 --- a/llvm/lib/Target/R600/SIInsertWaits.cpp +++ b/llvm/lib/Target/R600/SIInsertWaits.cpp @@ -134,9 +134,7 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { // LGKM may uses larger values if (TSFlags & SIInstrFlags::LGKM_CNT) { - MachineOperand &Op = MI.getOperand(0); - if (!Op.isReg()) - Op = MI.getOperand(1); + const MachineOperand &Op = MI.getOperand(0); assert(Op.isReg() && "First LGKM operand must be a register!"); unsigned Reg = Op.getReg(); |
