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| author | Eric Christopher <echristo@gmail.com> | 2015-03-11 18:43:21 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@gmail.com> | 2015-03-11 18:43:21 +0000 |
| commit | 6c5b511b4dd70fe47ad1f3e421bc231a90d6ee9b (patch) | |
| tree | de417ef956b29b7ea2d3a902acd81af2ef4ff28d /llvm/lib/Target/R600/SIInsertWaits.cpp | |
| parent | f4d9a5a964f64222f51c3b8b494588593f18eceb (diff) | |
| download | bcm5719-llvm-6c5b511b4dd70fe47ad1f3e421bc231a90d6ee9b.tar.gz bcm5719-llvm-6c5b511b4dd70fe47ad1f3e421bc231a90d6ee9b.zip | |
Remove the need to cache the subtarget in the R600 TargetRegisterInfo
classes.
llvm-svn: 231954
Diffstat (limited to 'llvm/lib/Target/R600/SIInsertWaits.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIInsertWaits.cpp | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/SIInsertWaits.cpp b/llvm/lib/Target/R600/SIInsertWaits.cpp index 50f20ac3619..90a37f17468 100644 --- a/llvm/lib/Target/R600/SIInsertWaits.cpp +++ b/llvm/lib/Target/R600/SIInsertWaits.cpp @@ -259,7 +259,8 @@ void SIInsertWaits::pushInstruction(MachineBasicBlock &MBB, return; } - if (TRI->ST.getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) { + if (MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() >= + AMDGPUSubtarget::VOLCANIC_ISLANDS) { // Any occurence of consecutive VMEM or SMEM instructions forms a VMEM // or SMEM clause, respectively. // @@ -412,7 +413,8 @@ Counters SIInsertWaits::handleOperands(MachineInstr &MI) { void SIInsertWaits::handleSendMsg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) { - if (TRI->ST.getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS) + if (MBB.getParent()->getSubtarget<AMDGPUSubtarget>().getGeneration() < + AMDGPUSubtarget::VOLCANIC_ISLANDS) return; // There must be "S_NOP 0" between an instruction writing M0 and S_SENDMSG. |
