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authorTom Stellard <thomas.stellard@amd.com>2014-03-24 16:07:25 +0000
committerTom Stellard <thomas.stellard@amd.com>2014-03-24 16:07:25 +0000
commit2c1c9de1515c1fa98426702196f4a9895a0450c5 (patch)
tree2f8f81804581675ea91f998fccd45f52aab4d983 /llvm/lib/Target/R600/R700Instructions.td
parent114777e47f4fd7cd9687ad4a3c9e5076fafdf07d (diff)
downloadbcm5719-llvm-2c1c9de1515c1fa98426702196f4a9895a0450c5.tar.gz
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R600: Reorganize tablegen instruction definitions
Each GPU family now has its own file. llvm-svn: 204615
Diffstat (limited to 'llvm/lib/Target/R600/R700Instructions.td')
-rw-r--r--llvm/lib/Target/R600/R700Instructions.td21
1 files changed, 21 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/R700Instructions.td b/llvm/lib/Target/R600/R700Instructions.td
new file mode 100644
index 00000000000..9aad85da4e9
--- /dev/null
+++ b/llvm/lib/Target/R600/R700Instructions.td
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+//===-- R700Instructions.td - R700 Instruction defs -------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// TableGen definitions for instructions which are:
+// - Available to R700 and newer VLIW4/VLIW5 GPUs
+// - Available only on R700 family GPUs.
+//
+//===----------------------------------------------------------------------===//
+
+def isR700 : Predicate<"Subtarget.getGeneration() == AMDGPUSubtarget::R700">;
+
+let Predicates = [isR700] in {
+ def SIN_r700 : SIN_Common<0x6E>;
+ def COS_r700 : COS_Common<0x6F>;
+}
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