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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-12-19 22:15:30 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-12-19 22:15:30 +0000 |
| commit | c3d7eeb6e561ecafd8e86fb52b287f0dcbd7453c (patch) | |
| tree | e4b2bd856d5f61571a28c0b76feaeba74b68b851 /llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | |
| parent | e8270225a29d22c40e4aee105229d64c7329aeee (diff) | |
| download | bcm5719-llvm-c3d7eeb6e561ecafd8e86fb52b287f0dcbd7453c.tar.gz bcm5719-llvm-c3d7eeb6e561ecafd8e86fb52b287f0dcbd7453c.zip | |
R600/SI: Make sure non-inline constants aren't folded into mubuf soffset operand
mubuf instructions now define the soffset field using the SCSrc_32
register class which indicates that only SGPRs and inline constants
are allowed.
llvm-svn: 224622
Diffstat (limited to 'llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index 999fd0dbc9a..4b693c4e8dc 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -90,8 +90,9 @@ bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, (AMDGPU::SSrc_64RegClassID == RegClass) || (AMDGPU::VSrc_32RegClassID == RegClass) || (AMDGPU::VSrc_64RegClassID == RegClass) || - (AMDGPU::VCSrc_32RegClassID == RegClass) || - (AMDGPU::VCSrc_64RegClassID == RegClass); + (AMDGPU::VCSrc_32RegClassID == RegClass) || + (AMDGPU::VCSrc_64RegClassID == RegClass) || + (AMDGPU::SCSrc_32RegClassID == RegClass); } uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const { |
