diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2013-02-07 19:39:40 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-02-07 19:39:40 +0000 |
| commit | 8909380e717d7f93f3f152aac81dbfade8cbd7b0 (patch) | |
| tree | 48d465d7c9d4482aa3cf8d83dea287b192e9b729 /llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | |
| parent | 26075d58a241c633739bf78dff90856bcbf992df (diff) | |
| download | bcm5719-llvm-8909380e717d7f93f3f152aac81dbfade8cbd7b0.tar.gz bcm5719-llvm-8909380e717d7f93f3f152aac81dbfade8cbd7b0.zip | |
R600/SI: simplify and fix SMRD encoding
The _SGPR variants where wrong.
Patch by: Christian König
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 174653
Diffstat (limited to 'llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp index b4bdb252895..8acc78fdbc5 100644 --- a/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp +++ b/llvm/lib/Target/R600/MCTargetDesc/SIMCCodeEmitter.cpp @@ -92,10 +92,6 @@ public: virtual unsigned GPR4AlignEncode(const MCInst &MI, unsigned OpNo, SmallVectorImpl<MCFixup> &Fixup) const; - /// \brief Encoding for SMRD indexed loads - virtual uint32_t SMRDmemriEncode(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixup) const; - /// \brief Post-Encoder method for VOP instructions virtual uint64_t VOPPostEncode(const MCInst &MI, uint64_t Value) const; @@ -183,36 +179,6 @@ unsigned SIMCCodeEmitter::GPR4AlignEncode(const MCInst &MI, return GPRAlign(MI, OpNo, 2); } -#define SMRD_OFFSET_MASK 0xff -#define SMRD_IMM_SHIFT 8 -#define SMRD_SBASE_MASK 0x3f -#define SMRD_SBASE_SHIFT 9 -/// This function is responsibe for encoding the offset -/// and the base ptr for SMRD instructions it should return a bit string in -/// this format: -/// -/// OFFSET = bits{7-0} -/// IMM = bits{8} -/// SBASE = bits{14-9} -/// -uint32_t SIMCCodeEmitter::SMRDmemriEncode(const MCInst &MI, unsigned OpNo, - SmallVectorImpl<MCFixup> &Fixup) const { - uint32_t Encoding; - - const MCOperand &OffsetOp = MI.getOperand(OpNo + 1); - - //XXX: Use this function for SMRD loads with register offsets - assert(OffsetOp.isImm()); - - Encoding = - (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK) - | (1 << SMRD_IMM_SHIFT) //XXX If the Offset is a register we shouldn't set this bit - | ((GPR2AlignEncode(MI, OpNo, Fixup) & SMRD_SBASE_MASK) << SMRD_SBASE_SHIFT) - ; - - return Encoding; -} - //===----------------------------------------------------------------------===// // Post Encoder Callbacks //===----------------------------------------------------------------------===// |
