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authorTom Stellard <thomas.stellard@amd.com>2013-08-06 23:08:28 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-08-06 23:08:28 +0000
commit2f7cdda57e31f925830fa626fc7278fca60fb3fa (patch)
tree5325853fc5f7087788b1193a3083ea448ee7ae03 /llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
parent4c0ffccbbf4ef58147bd8ae115cc9f6c3ef7d7a1 (diff)
downloadbcm5719-llvm-2f7cdda57e31f925830fa626fc7278fca60fb3fa.tar.gz
bcm5719-llvm-2f7cdda57e31f925830fa626fc7278fca60fb3fa.zip
R600/SI: Use VSrc_* register classes as the default classes for types
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies that used be emitted by isel like this: SGPR = COPY VGPR Will now be emitted like this: VSrC = COPY VGPR This patch also adds a pass that tries to identify and fix situations where a VGPR to SGPR copy may occur. Hopefully, these changes will make it impossible for the compiler to generate illegal VGPR to SGPR copies. llvm-svn: 187831
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUTargetMachine.cpp')
-rw-r--r--llvm/lib/Target/R600/AMDGPUTargetMachine.cpp2
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
index 1a304962e11..5ebc5f27dc4 100644
--- a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp
@@ -146,6 +146,8 @@ bool AMDGPUPassConfig::addPreRegAlloc() {
if (ST.getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
addPass(createR600VectorRegMerger(*TM));
+ } else {
+ addPass(createSIFixSGPRCopiesPass(*TM));
}
return false;
}
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