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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-07-21 16:55:33 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-07-21 16:55:33 +0000 |
| commit | 1aaad6970cee96c214cc663bc7ae2cecb6fd1e7c (patch) | |
| tree | fa24d65509767cb9ac91843d7c3d5c4e4644bc37 /llvm/lib/Target/R600/AMDGPUTargetMachine.cpp | |
| parent | ced7b43a064c696a98fd6f2a0a8e972a07e4cdeb (diff) | |
| download | bcm5719-llvm-1aaad6970cee96c214cc663bc7ae2cecb6fd1e7c.tar.gz bcm5719-llvm-1aaad6970cee96c214cc663bc7ae2cecb6fd1e7c.zip | |
R600/SI: Add instruction shrinking pass
This pass converts 64-bit instructions to 32-bit when possible.
llvm-svn: 213561
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUTargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUTargetMachine.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp index 23beb2576ac..56ba719e686 100644 --- a/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/R600/AMDGPUTargetMachine.cpp @@ -176,6 +176,7 @@ bool AMDGPUPassConfig::addPreRegAlloc() { // SIFixSGPRCopies can generate a lot of duplicate instructions, // so we need to run MachineCSE afterwards. addPass(&MachineCSEID); + addPass(createSIShrinkInstructionsPass()); initializeSIFixSGPRLiveRangesPass(*PassRegistry::getPassRegistry()); insertPass(&RegisterCoalescerID, &SIFixSGPRLiveRangesID); } @@ -185,6 +186,7 @@ bool AMDGPUPassConfig::addPreRegAlloc() { bool AMDGPUPassConfig::addPostRegAlloc() { const AMDGPUSubtarget &ST = TM->getSubtarget<AMDGPUSubtarget>(); + addPass(createSIShrinkInstructionsPass()); if (ST.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) { addPass(createSIInsertWaits(*TM)); } |
