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authorTom Stellard <thomas.stellard@amd.com>2015-01-20 19:33:04 +0000
committerTom Stellard <thomas.stellard@amd.com>2015-01-20 19:33:04 +0000
commite99fb65d87d69e805c061cbbc295708d3c62af5a (patch)
tree695b11888ea7eb58c0ae81721e35878ffc0f7a4d /llvm/lib/Target/R600/AMDGPUSubtarget.cpp
parent021053f500e0f232335ec013556f4ff362d83d65 (diff)
downloadbcm5719-llvm-e99fb65d87d69e805c061cbbc295708d3c62af5a.tar.gz
bcm5719-llvm-e99fb65d87d69e805c061cbbc295708d3c62af5a.zip
R600/SI: Add subtarget feature to enable VGPR spilling for all shader types
This is disabled by default, but can be enabled with the subtarget feature: 'vgpr-spilling' llvm-svn: 226597
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUSubtarget.cpp')
-rw-r--r--llvm/lib/Target/R600/AMDGPUSubtarget.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp
index 597e558e663..9f22adcc7f6 100644
--- a/llvm/lib/Target/R600/AMDGPUSubtarget.cpp
+++ b/llvm/lib/Target/R600/AMDGPUSubtarget.cpp
@@ -18,6 +18,7 @@
#include "R600MachineScheduler.h"
#include "SIISelLowering.h"
#include "SIInstrInfo.h"
+#include "SIMachineFunctionInfo.h"
#include "llvm/ADT/SmallString.h"
using namespace llvm;
@@ -78,6 +79,7 @@ AMDGPUSubtarget::AMDGPUSubtarget(StringRef TT, StringRef GPU, StringRef FS,
FlatAddressSpace(false), EnableIRStructurizer(true),
EnablePromoteAlloca(false), EnableIfCvt(true),
EnableLoadStoreOpt(false), WavefrontSize(0), CFALUBug(false), LocalMemorySize(0),
+ EnableVGPRSpilling(false),
DL(computeDataLayout(initializeSubtargetDependencies(GPU, FS))),
FrameLowering(TargetFrameLowering::StackGrowsUp,
64 * 16, // Maximum stack alignment (long16)
@@ -113,3 +115,8 @@ unsigned AMDGPUSubtarget::getAmdKernelCodeChipID() const {
case SEA_ISLANDS: return 12;
}
}
+
+bool AMDGPUSubtarget::isVGPRSpillingEnabled(
+ const SIMachineFunctionInfo *MFI) const {
+ return MFI->getShaderType() == ShaderType::COMPUTE || EnableVGPRSpilling;
+}
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