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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 14:18:14 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-12 14:18:14 +0000 |
| commit | fc92e774453576278ddf694bb9a3cb52c366cd6d (patch) | |
| tree | 2b71cc3a7b49b7458e274d469fd45775c271e32d /llvm/lib/Target/R600/AMDGPUInstrInfo.td | |
| parent | d33d7f15a26208225b7cfbbe5eda2e28cdf82a11 (diff) | |
| download | bcm5719-llvm-fc92e774453576278ddf694bb9a3cb52c366cd6d.tar.gz bcm5719-llvm-fc92e774453576278ddf694bb9a3cb52c366cd6d.zip | |
R600/SI: Remove explicit m0 operand from s_sendmsg
Instead add m0 as an implicit operand. This allows us to avoid using
the M0Reg register class and eliminates a number of unnecessary spills
when using s_sendmsg instructions. This impacts one shader in the
shader-db:
SGPRS: 48 -> 40 (-16.67 %)
VGPRS: 112 -> 108 (-3.57 %)
Code Size: 40132 -> 38796 (-3.33 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Scratch: 2048 -> 0 (-100.00 %) bytes per wave
llvm-svn: 237133
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/R600/AMDGPUInstrInfo.td | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUInstrInfo.td b/llvm/lib/Target/R600/AMDGPUInstrInfo.td index d72cb1d7f8c..e251cb48e0d 100644 --- a/llvm/lib/Target/R600/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/R600/AMDGPUInstrInfo.td @@ -219,6 +219,10 @@ def AMDGPUmad_i24 : SDNode<"AMDGPUISD::MAD_I24", AMDGPUDTIntTernaryOp, [] >; +def AMDGPUsendmsg : SDNode<"AMDGPUISD::SENDMSG", + SDTypeProfile<0, 1, [SDTCisInt<0>]>, + [SDNPHasChain, SDNPInGlue]>; + //===----------------------------------------------------------------------===// // Flow Control Profile Types //===----------------------------------------------------------------------===// |
