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authorJan Vesely <jan.vesely@rutgers.edu>2015-04-12 23:45:01 +0000
committerJan Vesely <jan.vesely@rutgers.edu>2015-04-12 23:45:01 +0000
commit811ef52db7a6a3eda18c59ed92bff015e45bf20b (patch)
tree4c0d5afad297d8fbc5680c0de67578564ade9016 /llvm/lib/Target/R600/AMDGPUISelLowering.cpp
parent9e0c890f3ee7908a61375678c5910a35dce85d85 (diff)
downloadbcm5719-llvm-811ef52db7a6a3eda18c59ed92bff015e45bf20b.tar.gz
bcm5719-llvm-811ef52db7a6a3eda18c59ed92bff015e45bf20b.zip
R600: remove manual BFE optimization
Fixed since r233079 Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> reviewer: arsenm llvm-svn: 234715
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUISelLowering.cpp')
-rw-r--r--llvm/lib/Target/R600/AMDGPUISelLowering.cpp10
1 files changed, 2 insertions, 8 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
index 62a33fad64b..ad557077f3f 100644
--- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -1685,14 +1685,8 @@ void AMDGPUTargetLowering::LowerUDIVREM64(SDValue Op,
const unsigned bitPos = halfBitWidth - i - 1;
SDValue POS = DAG.getConstant(bitPos, HalfVT);
// Get value of high bit
- // TODO: Remove the BFE part when the optimization is fixed
- SDValue HBit;
- if (halfBitWidth == 32 && Subtarget->hasBFE()) {
- HBit = DAG.getNode(AMDGPUISD::BFE_U32, DL, HalfVT, LHS_Lo, POS, one);
- } else {
- HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
- HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
- }
+ SDValue HBit = DAG.getNode(ISD::SRL, DL, HalfVT, LHS_Lo, POS);
+ HBit = DAG.getNode(ISD::AND, DL, HalfVT, HBit, one);
HBit = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, HBit);
// Shift
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