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authorMatt Arsenault <Matthew.Arsenault@amd.com>2015-02-14 04:22:00 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2015-02-14 04:22:00 +0000
commit1bc9d95047f45a014832418cf1f3edd9ff92bd12 (patch)
tree8fb0dc17f939272da3b6d5383281cc9d4f01c09b /llvm/lib/Target/R600/AMDGPUISelLowering.cpp
parent6e26b8d8541357e53d04f90ba8bc9635e5fe1004 (diff)
downloadbcm5719-llvm-1bc9d95047f45a014832418cf1f3edd9ff92bd12.tar.gz
bcm5719-llvm-1bc9d95047f45a014832418cf1f3edd9ff92bd12.zip
R600/SI: Fix implicit vcc operand to v_div_fmas_*
This should allow finally fixing the f64 fdiv implementation. Test is disabled for VI since there seems to be a problem with one of the buffer load instructions on it. llvm-svn: 229236
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUISelLowering.cpp')
-rw-r--r--llvm/lib/Target/R600/AMDGPUISelLowering.cpp5
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
index d577d689f66..d96f03aaeb0 100644
--- a/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/R600/AMDGPUISelLowering.cpp
@@ -907,10 +907,9 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
}
case Intrinsic::AMDGPU_div_fmas:
- // FIXME: Dropping bool parameter. Work is needed to support the implicit
- // read from VCC.
return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
- Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
+ Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
+ Op.getOperand(4));
case Intrinsic::AMDGPU_div_fixup:
return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
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