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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-05-14 09:28:21 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-05-14 09:28:21 +0000
commitd454ec0c31b39e269c05f274bb5dc674f77004fa (patch)
tree5e63bb7fcb20559af14d8c777cde0f6f3b6944cb /llvm/lib/Target/R600/AMDGPUFrameLowering.cpp
parent24db0f0afd425fdb0854d3d6a6e04f87c76dd27f (diff)
downloadbcm5719-llvm-d454ec0c31b39e269c05f274bb5dc674f77004fa.tar.gz
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[SystemZ] Match operands to fields by name rather than by order
The SystemZ port currently relies on the order of the instruction operands matching the order of the instruction field lists. This isn't desirable for disassembly, where the two are matched only by name. E.g. the R1 and R2 fields of an RR instruction should have corresponding R1 and R2 operands. The main complication is that addresses are compound operands, and as far as I know there is no mechanism to allow individual suboperands to be selected by name in "let Inst{...} = ..." assignments. Luckily it doesn't really matter though. The SystemZ instruction encoding groups all address fields together in a predictable order, so it's just as valid to see the entire compound address operand as a single field. That's the approach taken in this patch. Matching by name in turn means that the operands to COPY SIGN and CONVERT TO FIXED instructions can be given in natural order. (It was easier to do this at the same time as the rename, since otherwise the intermediate step was too confusing.) No functional change intended. llvm-svn: 181769
Diffstat (limited to 'llvm/lib/Target/R600/AMDGPUFrameLowering.cpp')
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