[PowerPC] Revert r310346 (and followups r310356 & r310424) which

introduce a miscompile bug.

There appears to be a bug where the generated code to extract the sign
bit doesn't work correctly for 32-bit inputs. I've replied to the
original commit pointing out the problem. I think I see by inspection
(and reading the manual for PPC) how to fix this, but I can't be 100%
confident and I also don't know what the best way to test this is.
Currently it seems nearly impossible to get the backend to hit this code
path, but the patch autohr is likely in a better position to craft such
test cases than I am, and based on where the bug is it should be easily
done.

Original commit message for r310346:
"""
[PowerPC] Eliminate compares - add i32 sext/zext handling for SETLE/SETGE

Adds handling for SETLE/SETGE comparisons on i32 values. Furthermore, it
adds the handling for the special case where RHS == 0.

Differential Revision: https://reviews.llvm.org/D34048
"""

llvm-svn: 310809

1 files changed, 0 insertions, 132 deletions

diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index c994ea102a8..4867f77bdc5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -282,11 +282,6 @@ private:
     // SExtInvert - invert the condition code, sign-extend value
     enum SetccInGPROpts { ZExtOrig, ZExtInvert, SExtOrig, SExtInvert };
 
-    // Comparisons against zero to emit GPR code sequences for. Each of these
-    // sequences may need to be emitted for two or more equivalent patterns.
-    // For example (a >= 0) == (a > -1).
-    enum ZeroCompare { GEZExt, GESExt, LEZExt, LESExt };
-
     bool trySETCC(SDNode *N);
     bool tryEXTEND(SDNode *N);
     bool tryLogicOpOfCompares(SDNode *N);
@@ -294,8 +289,6 @@ private:
     SDValue signExtendInputIfNeeded(SDValue Input);
     SDValue zeroExtendInputIfNeeded(SDValue Input);
     SDValue addExtOrTrunc(SDValue NatWidthRes, ExtOrTruncConversion Conv);
-    SDValue getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
-                                           ZeroCompare CmpTy);
     SDValue get32BitZExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                 int64_t RHSValue, SDLoc dl);
     SDValue get32BitSExtCompare(SDValue LHS, SDValue RHS, ISD::CondCode CC,
@@ -2804,77 +2797,6 @@ SDValue PPCDAGToDAGISel::addExtOrTrunc(SDValue NatWidthRes,
                                         NatWidthRes, SubRegIdx), 0);
 }
 
-// Produce a GPR sequence for compound comparisons (<=, >=) against zero.
-// Handle both zero-extensions and sign-extensions.
-SDValue PPCDAGToDAGISel::getCompoundZeroComparisonInGPR(SDValue LHS, SDLoc dl,
-                                                        ZeroCompare CmpTy) {
-  EVT InVT = LHS.getValueType();
-  bool Is32Bit = InVT == MVT::i32;
-  SDValue ToExtend;
-
-  // Produce the value that needs to be either zero or sign extended.
-  switch (CmpTy) {
-  case ZeroCompare::GEZExt:
-  case ZeroCompare::GESExt:
-    ToExtend = SDValue(CurDAG->getMachineNode(Is32Bit ? PPC::NOR : PPC::NOR8,
-                                              dl, InVT, LHS, LHS), 0);
-    break;
-  case ZeroCompare::LEZExt:
-  case ZeroCompare::LESExt: {
-    if (Is32Bit) {
-      SDValue Neg =
-        SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, LHS), 0);
-      ToExtend =
-        SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
-                                       Neg, getI64Imm(1, dl),
-                                       getI64Imm(63, dl)), 0);
-    } else {
-      SDValue Addi =
-        SDValue(CurDAG->getMachineNode(PPC::ADDI8, dl, MVT::i64, LHS,
-                                       getI64Imm(~0ULL, dl)), 0);
-      ToExtend = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
-                                                Addi, LHS), 0);
-    }
-    break;
-  }
-  }
-
-  // For 64-bit sequences, the extensions are the same for the GE/LE cases.
-  if (!Is32Bit &&
-      (CmpTy == ZeroCompare::GEZExt || CmpTy == ZeroCompare::LEZExt))
-    return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64,
-                                          ToExtend, getI64Imm(1, dl),
-                                          getI64Imm(63, dl)), 0);
-  if (!Is32Bit &&
-      (CmpTy == ZeroCompare::GESExt || CmpTy == ZeroCompare::LESExt))
-    return SDValue(CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, ToExtend,
-                                          getI64Imm(63, dl)), 0);
-
-  assert(Is32Bit && "Should have handled the 32-bit sequences above.");
-  // For 32-bit sequences, the extensions differ between GE/LE cases.
-  switch (CmpTy) {
-  case ZeroCompare::GEZExt: {
-    SDValue ShiftOps[] =
-      { ToExtend, getI32Imm(1, dl), getI32Imm(31, dl), getI32Imm(31, dl) };
-    return SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
-                                          ShiftOps), 0);
-  }
-  case ZeroCompare::GESExt:
-    return SDValue(CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, ToExtend,
-                                          getI32Imm(31, dl)), 0);
-  case ZeroCompare::LEZExt:
-    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, ToExtend,
-                   getI32Imm(1, dl)), 0);
-  case ZeroCompare::LESExt:
-    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, ToExtend,
-                                          getI32Imm(-1, dl)), 0);
-  }
-
-  // The above case covers all the enumerators so it can't have a default clause
-  // to avoid compiler warnings.
-  llvm_unreachable("Unknown zero-comparison type.");
-}
-
 /// Produces a zero-extended result of comparing two 32-bit values according to
 /// the passed condition code.
 SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
@@ -2909,32 +2831,6 @@ SDValue PPCDAGToDAGISel::get32BitZExtCompare(SDValue LHS, SDValue RHS,
     return SDValue(CurDAG->getMachineNode(PPC::XORI, dl, MVT::i32, Shift,
                                           getI32Imm(1, dl)), 0);
   }
-  case ISD::SETGE: {
-    // (zext (setcc %a, %b, setge)) -> (xor (lshr (sub %a, %b), 63), 1)
-    // (zext (setcc %a, 0, setge))  -> (lshr (~ %a), 31)
-    if(IsRHSZero)
-      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GEZExt);
-
-    // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
-    // by swapping inputs and falling through.
-    std::swap(LHS, RHS);
-    ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
-    IsRHSZero = RHSConst && RHSConst->isNullValue();
-    LLVM_FALLTHROUGH;
-  }
-  case ISD::SETLE: {
-    // (zext (setcc %a, %b, setle)) -> (xor (lshr (sub %b, %a), 63), 1)
-    // (zext (setcc %a, 0, setle))  -> (xor (lshr (- %a), 63), 1)
-    if(IsRHSZero)
-      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LEZExt);
-    SDValue Sub =
-      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, LHS, RHS), 0);
-    SDValue Shift =
-      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32, Sub,
-                                     getI64Imm(1, dl), getI64Imm(63, dl)), 0);
-    return SDValue(CurDAG->getMachineNode(PPC::XORI, dl,
-                   MVT::i32, Shift, getI32Imm(1, dl)), 0);
-  }
   }
 }
 
@@ -2982,34 +2878,6 @@ SDValue PPCDAGToDAGISel::get32BitSExtCompare(SDValue LHS, SDValue RHS,
                                      getI32Imm(1, dl)), 0);
     return SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Xori), 0);
   }
-  case ISD::SETGE: {
-    // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %a, %b), 63), -1)
-    // (sext (setcc %a, 0, setge))  -> (ashr (~ %a), 31)
-    if (IsRHSZero)
-      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::GESExt);
-
-    // Not a special case (i.e. RHS == 0). Handle (%a >= %b) as (%b <= %a)
-    // by swapping inputs and falling through.
-    std::swap(LHS, RHS);
-    ConstantSDNode *RHSConst = dyn_cast<ConstantSDNode>(RHS);
-    IsRHSZero = RHSConst && RHSConst->isNullValue();
-    LLVM_FALLTHROUGH;
-  }
-  case ISD::SETLE: {
-    // (sext (setcc %a, %b, setge)) -> (add (lshr (sub %b, %a), 63), -1)
-    // (sext (setcc %a, 0, setle))  -> (add (lshr (- %a), 63), -1)
-    if (IsRHSZero)
-      return getCompoundZeroComparisonInGPR(LHS, dl, ZeroCompare::LESExt);
-    SDValue SUBFNode =
-      SDValue(CurDAG->getMachineNode(PPC::SUBF, dl, MVT::i32, MVT::Glue,
-                                     LHS, RHS), 0);
-    SDValue Srdi =
-      SDValue(CurDAG->getMachineNode(PPC::RLDICL_32, dl, MVT::i32,
-                                     SUBFNode, getI64Imm(1, dl),
-                                     getI64Imm(63, dl)), 0);
-    return SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Srdi,
-                                          getI32Imm(-1, dl)), 0);
-  }
   }
 }