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authorJinsong Ji <jji@us.ibm.com>2019-12-31 16:24:35 +0000
committerJinsong Ji <jji@us.ibm.com>2019-12-31 16:24:40 +0000
commitfcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2 (patch)
treeac18051cb04fef5d6031e913b75f4887b28b05ac /llvm/lib/Target/PowerPC
parentff429c5eaf79529aacdc15582c90c0915080e082 (diff)
downloadbcm5719-llvm-fcbf05bbdccc8a32f6a80316ea1c13be7e7eeae2.tar.gz
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[PowerPC][NFC] Fix clang-tidy warning
Reported by https://results.llvm-merge-guard.org/amd64_debian_testing_clang8-726/clang-tidy.txt /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11672:10: warning: invalid case style for variable 'isEQ' [readability-identifier-naming] bool isEQ = (MI.getOpcode() == PPC::ANDI_rec_1_EQ_BIT || ^~~~ IsEq /mnt/disks/ssd0/agent/workspace/amd64_debian_testing_clang8/llvm/lib/Target/PowerPC/PPCISelLowering.cpp:11679:14: warning: invalid case style for variable 'dl' [readability-identifier-naming] DebugLoc dl = MI.getDebugLoc(); ^~ Dl
Diffstat (limited to 'llvm/lib/Target/PowerPC')
-rw-r--r--llvm/lib/Target/PowerPC/PPCISelLowering.cpp10
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index cbbf1324620..9fab29dded7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -11669,20 +11669,20 @@ PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MI.getOpcode() == PPC::ANDIo_1_GT_BIT8)
? PPC::ANDI8o
: PPC::ANDIo;
- bool isEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
+ bool IsEQ = (MI.getOpcode() == PPC::ANDIo_1_EQ_BIT ||
MI.getOpcode() == PPC::ANDIo_1_EQ_BIT8);
MachineRegisterInfo &RegInfo = F->getRegInfo();
Register Dest = RegInfo.createVirtualRegister(
Opcode == PPC::ANDIo ? &PPC::GPRCRegClass : &PPC::G8RCRegClass);
- DebugLoc dl = MI.getDebugLoc();
- BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
+ DebugLoc Dl = MI.getDebugLoc();
+ BuildMI(*BB, MI, Dl, TII->get(Opcode), Dest)
.addReg(MI.getOperand(1).getReg())
.addImm(1);
- BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
+ BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
MI.getOperand(0).getReg())
- .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
+ .addReg(IsEQ ? PPC::CR0EQ : PPC::CR0GT);
} else if (MI.getOpcode() == PPC::TCHECK_RET) {
DebugLoc Dl = MI.getDebugLoc();
MachineRegisterInfo &RegInfo = F->getRegInfo();
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