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| author | QingShan Zhang <qshanz@cn.ibm.com> | 2019-12-11 07:25:57 +0000 |
|---|---|---|
| committer | QingShan Zhang <qshanz@cn.ibm.com> | 2019-12-11 07:25:57 +0000 |
| commit | f99297176cd9507393b69029406080de01ae41c7 (patch) | |
| tree | a2955232f6d349a3a5e16749825fd8cced61f242 /llvm/lib/Target/PowerPC | |
| parent | d4345636e678ccab8a87b09cdad9129e54c23100 (diff) | |
| download | bcm5719-llvm-f99297176cd9507393b69029406080de01ae41c7.tar.gz bcm5719-llvm-f99297176cd9507393b69029406080de01ae41c7.zip | |
[PowerPC] Exploitate the Vector Integer Average Instructions
PowerPC has instruction to do the semantics of this piece of code:
vector int foo(vector int m, vector int n) {
return (m + n + 1) >> 1;
}
This patch is adding the match rule to select it.
Differential Revision: https://reviews.llvm.org/D71002
Diffstat (limited to 'llvm/lib/Target/PowerPC')
| -rw-r--r-- | llvm/lib/Target/PowerPC/PPCInstrAltivec.td | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td index 26c506ef4e2..649c44f2a09 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrAltivec.td +++ b/llvm/lib/Target/PowerPC/PPCInstrAltivec.td @@ -261,6 +261,11 @@ def vecspltisw : PatLeaf<(build_vector), [{ return PPC::get_VSPLTI_elt(N, 4, *CurDAG).getNode() != nullptr; }], VSPLTISW_get_imm>; +def immEQOneV : PatLeaf<(build_vector), [{ + if (ConstantSDNode *C = cast<BuildVectorSDNode>(N)->getConstantSplatNode()) + return C->isOne(); + return false; +}]>; //===----------------------------------------------------------------------===// // Helpers for defining instructions that directly correspond to intrinsics. @@ -1092,6 +1097,20 @@ def : Pat<(v4f32 (vselect v4i32:$vA, v4f32:$vB, v4f32:$vC)), def : Pat<(v2f64 (vselect v2i64:$vA, v2f64:$vB, v2f64:$vC)), (VSEL $vC, $vB, $vA)>; +// Vector Integer Average Instructions +def : Pat<(v4i32 (sra (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), + (v4i32 (immEQOneV)))), (v4i32 (VAVGSW $vA, $vB))>; +def : Pat<(v8i16 (sra (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), + (v8i16 (immEQOneV)))), (v8i16 (VAVGSH $vA, $vB))>; +def : Pat<(v16i8 (sra (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), + (v16i8 (immEQOneV)))), (v16i8 (VAVGSB $vA, $vB))>; +def : Pat<(v4i32 (srl (sub v4i32:$vA, (vnot_ppc v4i32:$vB)), + (v4i32 (immEQOneV)))), (v4i32 (VAVGUW $vA, $vB))>; +def : Pat<(v8i16 (srl (sub v8i16:$vA, (v8i16 (bitconvert(vnot_ppc v4i32:$vB)))), + (v8i16 (immEQOneV)))), (v8i16 (VAVGUH $vA, $vB))>; +def : Pat<(v16i8 (srl (sub v16i8:$vA, (v16i8 (bitconvert(vnot_ppc v4i32:$vB)))), + (v16i8 (immEQOneV)))), (v16i8 (VAVGUB $vA, $vB))>; + } // end HasAltivec def HasP8Altivec : Predicate<"PPCSubTarget->hasP8Altivec()">; |

